| Message ID | 20191031142112.12431-9-frieder.schrempf@kontron.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for more Kontron i.MX6UL/ULL SoMs and boards | expand |
On Thu, Oct 31, 2019 at 02:24:24PM +0000, Schrempf Frieder wrote: > From: Frieder Schrempf <frieder.schrempf@kontron.de> > > The ECSPI1 is not used for a FRAM chip, so remove the comment. > While at it, also change some whitespaces to tabs to comply with the > indentation style of the rest of the file. > > Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> > Fixes: 1ea4b76cdfde ("ARM: dts: imx6ul-kontron-n6310: Add Kontron i.MX6UL N6310 SoM and boards") It's not a bug fix. Shawn > --- > arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi | 13 ++++++------- > 1 file changed, 6 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi > index d3eb21aa9014..e18a8bd239be 100644 > --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi > +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi > @@ -256,7 +256,6 @@ > >; > }; > > - /* FRAM */ > pinctrl_ecspi1: ecspi1grp { > fsl,pins = < > MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 > @@ -281,8 +280,8 @@ > > pinctrl_enet2_mdio: enet2mdiogrp { > fsl,pins = < > - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 > - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 > + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 > + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 > >; > }; > > @@ -295,10 +294,10 @@ > > pinctrl_gpio: gpiogrp { > fsl,pins = < > - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ > - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ > - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ > - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ > + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ > + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ > + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ > + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ > >; > }; > > -- > 2.17.1
On 04.11.19 08:33, Shawn Guo wrote: > On Thu, Oct 31, 2019 at 02:24:24PM +0000, Schrempf Frieder wrote: >> From: Frieder Schrempf <frieder.schrempf@kontron.de> >> >> The ECSPI1 is not used for a FRAM chip, so remove the comment. >> While at it, also change some whitespaces to tabs to comply with the >> indentation style of the rest of the file. >> >> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> >> Fixes: 1ea4b76cdfde ("ARM: dts: imx6ul-kontron-n6310: Add Kontron i.MX6UL N6310 SoM and boards") > > It's not a bug fix. Right. > > Shawn > >> --- >> arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi | 13 ++++++------- >> 1 file changed, 6 insertions(+), 7 deletions(-) >> >> diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi >> index d3eb21aa9014..e18a8bd239be 100644 >> --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi >> +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi >> @@ -256,7 +256,6 @@ >> >; >> }; >> >> - /* FRAM */ >> pinctrl_ecspi1: ecspi1grp { >> fsl,pins = < >> MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 >> @@ -281,8 +280,8 @@ >> >> pinctrl_enet2_mdio: enet2mdiogrp { >> fsl,pins = < >> - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 >> - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 >> + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 >> + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 >> >; >> }; >> >> @@ -295,10 +294,10 @@ >> >> pinctrl_gpio: gpiogrp { >> fsl,pins = < >> - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ >> - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ >> - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ >> - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ >> + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ >> + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ >> + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ >> + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ >> >; >> }; >> >> -- >> 2.17.1
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi index d3eb21aa9014..e18a8bd239be 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi @@ -256,7 +256,6 @@ >; }; - /* FRAM */ pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 @@ -281,8 +280,8 @@ pinctrl_enet2_mdio: enet2mdiogrp { fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 >; }; @@ -295,10 +294,10 @@ pinctrl_gpio: gpiogrp { fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ >; };