From patchwork Fri Nov 8 14:42:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11235039 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 556B71599 for ; Fri, 8 Nov 2019 14:45:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2707B20659 for ; Fri, 8 Nov 2019 14:45:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Ey5Y1YW0" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2707B20659 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=gXNSzQBuDXoR+PssXLS2dVz9T8NDioith8eZVWcDx3I=; b=Ey5Y1YW0FtXTZeRRU02Kx/W+nN t5IsnU39CpKJN9IV9JkTohN9ff/VnAiGcJr6bznPccdM6NuUaTwhTbu2wGx0v9W/WbLDFwgD9zdCR ILr/MIlKkn8vNCTwH+cOU9+9fVGPU7V+mYVS11bPVryZ60C+yR44A49kRnyulcKS5VHeCuYdtDIqD lHuDfW1dslyKX3p0UbQeU+z3ilGXZ86/xw1AkTzTlg9kt/a2o0f1vicFqIVpd7piMNJg75CZM2262 1ooq5GcPmFK/WE9peGinbS8PsXk120IQ2Hk9FwLQjsbbNyt2ms3HKOQVddMGv9LD9NrLI1fv0pUZb XTfF0qEQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iT5WN-00032L-K8; Fri, 08 Nov 2019 14:45:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iT5Te-0007dG-Qt for linux-arm-kernel@lists.infradead.org; Fri, 08 Nov 2019 14:43:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 88F9446A; Fri, 8 Nov 2019 06:43:06 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6BB433F719; Fri, 8 Nov 2019 06:43:05 -0800 (PST) From: Andre Przywara To: Andrew Jones , Paolo Bonzini Subject: [kvm-unit-tests PATCH 12/17] arm: gic: Change gic_read_iar() to take group parameter Date: Fri, 8 Nov 2019 14:42:35 +0000 Message-Id: <20191108144240.204202-13-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191108144240.204202-1-andre.przywara@arm.com> References: <20191108144240.204202-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191108_064307_019822_BA067356 X-CRM114-Status: GOOD ( 15.87 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Alexandru Elisei , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Acknowledging a GIC group 0 interrupt requires us to use a different system register on GICv3. To allow us to differentiate the two groups later, add a group parameter to gic_read_iar(). For GICv2 we can use the same CPU interface register to acknowledge group 0 as well, so we ignore the parameter here. For now this is still using group 1 on every caller. Signed-off-by: Andre Przywara --- arm/gic.c | 4 ++-- arm/micro-bench.c | 2 +- arm/pl031.c | 2 +- arm/timer.c | 2 +- lib/arm/asm/arch_gicv3.h | 11 +++++++++-- lib/arm/asm/gic-v2.h | 2 +- lib/arm/asm/gic-v3.h | 2 +- lib/arm/asm/gic.h | 2 +- lib/arm/gic-v2.c | 3 ++- lib/arm/gic.c | 6 +++--- lib/arm64/asm/arch_gicv3.h | 10 ++++++++-- 11 files changed, 30 insertions(+), 16 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index a0511e5..7be13a6 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -156,7 +156,7 @@ static void check_irqnr(u32 irqnr, int expected) static void irq_handler(struct pt_regs *regs __unused) { - u32 irqstat = gic_read_iar(); + u32 irqstat = gic_read_iar(1); u32 irqnr = gic_iar_irqnr(irqstat); if (irqnr == GICC_INT_SPURIOUS) { @@ -288,7 +288,7 @@ static struct gic gicv3 = { static void ipi_clear_active_handler(struct pt_regs *regs __unused) { - u32 irqstat = gic_read_iar(); + u32 irqstat = gic_read_iar(1); u32 irqnr = gic_iar_irqnr(irqstat); if (irqnr != GICC_INT_SPURIOUS) { diff --git a/arm/micro-bench.c b/arm/micro-bench.c index 4612f41..2bfee68 100644 --- a/arm/micro-bench.c +++ b/arm/micro-bench.c @@ -33,7 +33,7 @@ static void ipi_irq_handler(struct pt_regs *regs) { ipi_ready = false; ipi_received = true; - gic_write_eoir(gic_read_iar()); + gic_write_eoir(gic_read_iar(1)); ipi_ready = true; } diff --git a/arm/pl031.c b/arm/pl031.c index 5672f36..5be3d76 100644 --- a/arm/pl031.c +++ b/arm/pl031.c @@ -134,7 +134,7 @@ static void gic_irq_unmask(void) static void irq_handler(struct pt_regs *regs) { - u32 irqstat = gic_read_iar(); + u32 irqstat = gic_read_iar(1); u32 irqnr = gic_iar_irqnr(irqstat); gic_write_eoir(irqstat); diff --git a/arm/timer.c b/arm/timer.c index 0b808d5..e5cc3b4 100644 --- a/arm/timer.c +++ b/arm/timer.c @@ -150,7 +150,7 @@ static void set_timer_irq_enabled(struct timer_info *info, bool enabled) static void irq_handler(struct pt_regs *regs) { struct timer_info *info; - u32 irqstat = gic_read_iar(); + u32 irqstat = gic_read_iar(1); u32 irqnr = gic_iar_irqnr(irqstat); if (irqnr != GICC_INT_SPURIOUS) diff --git a/lib/arm/asm/arch_gicv3.h b/lib/arm/asm/arch_gicv3.h index 45b6096..52e7bba 100644 --- a/lib/arm/asm/arch_gicv3.h +++ b/lib/arm/asm/arch_gicv3.h @@ -16,6 +16,7 @@ #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) #define ICC_SGI1R __ACCESS_CP15_64(0, c12) +#define ICC_IAR0 __ACCESS_CP15(c12, 0, c8, 0) #define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0) #define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1) #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7) @@ -30,9 +31,15 @@ static inline void gicv3_write_sgi1r(u64 val) write_sysreg(val, ICC_SGI1R); } -static inline u32 gicv3_read_iar(void) +static inline u32 gicv3_read_iar(int group) { - u32 irqstat = read_sysreg(ICC_IAR1); + u32 irqstat; + + if (group == 0) + irqstat = read_sysreg(ICC_IAR0); + else + irqstat = read_sysreg(ICC_IAR1); + dsb(sy); return irqstat; } diff --git a/lib/arm/asm/gic-v2.h b/lib/arm/asm/gic-v2.h index 1fcfd43..d50c610 100644 --- a/lib/arm/asm/gic-v2.h +++ b/lib/arm/asm/gic-v2.h @@ -32,7 +32,7 @@ extern struct gicv2_data gicv2_data; extern int gicv2_init(void); extern void gicv2_enable_defaults(void); -extern u32 gicv2_read_iar(void); +extern u32 gicv2_read_iar(int group); extern u32 gicv2_iar_irqnr(u32 iar); extern void gicv2_write_eoir(u32 irqstat); extern void gicv2_ipi_send_single(int irq, int cpu); diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 0a29610..ca19110 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -69,7 +69,7 @@ extern struct gicv3_data gicv3_data; extern int gicv3_init(void); extern void gicv3_enable_defaults(void); -extern u32 gicv3_read_iar(void); +extern u32 gicv3_read_iar(int group); extern u32 gicv3_iar_irqnr(u32 iar); extern void gicv3_write_eoir(u32 irqstat); extern void gicv3_ipi_send_single(int irq, int cpu); diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 21cdb58..09663e7 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -68,7 +68,7 @@ extern void gic_enable_defaults(void); * below will work with any supported gic version. */ extern int gic_version(void); -extern u32 gic_read_iar(void); +extern u32 gic_read_iar(int group); extern u32 gic_iar_irqnr(u32 iar); extern void gic_write_eoir(u32 irqstat); extern void gic_ipi_send_single(int irq, int cpu); diff --git a/lib/arm/gic-v2.c b/lib/arm/gic-v2.c index dc6a97c..b60967e 100644 --- a/lib/arm/gic-v2.c +++ b/lib/arm/gic-v2.c @@ -26,8 +26,9 @@ void gicv2_enable_defaults(void) writel(GICC_ENABLE, cpu_base + GICC_CTLR); } -u32 gicv2_read_iar(void) +u32 gicv2_read_iar(int group) { + /* GICv2 acks both group0 and group1 IRQs with the same register. */ return readl(gicv2_cpu_base() + GICC_IAR); } diff --git a/lib/arm/gic.c b/lib/arm/gic.c index cf4e811..b51eff5 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -12,7 +12,7 @@ struct gicv3_data gicv3_data; struct gic_common_ops { void (*enable_defaults)(void); - u32 (*read_iar)(void); + u32 (*read_iar)(int group); u32 (*iar_irqnr)(u32 iar); void (*write_eoir)(u32 irqstat); void (*ipi_send_single)(int irq, int cpu); @@ -117,10 +117,10 @@ void gic_enable_defaults(void) gic_common_ops->enable_defaults(); } -u32 gic_read_iar(void) +u32 gic_read_iar(int group) { assert(gic_common_ops && gic_common_ops->read_iar); - return gic_common_ops->read_iar(); + return gic_common_ops->read_iar(group); } u32 gic_iar_irqnr(u32 iar) diff --git a/lib/arm64/asm/arch_gicv3.h b/lib/arm64/asm/arch_gicv3.h index a7994ec..876e1fc 100644 --- a/lib/arm64/asm/arch_gicv3.h +++ b/lib/arm64/asm/arch_gicv3.h @@ -11,6 +11,7 @@ #include #define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) +#define ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) #define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) #define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) #define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) @@ -38,10 +39,15 @@ static inline void gicv3_write_sgi1r(u64 val) asm volatile("msr_s " xstr(ICC_SGI1R_EL1) ", %0" : : "r" (val)); } -static inline u32 gicv3_read_iar(void) +static inline u32 gicv3_read_iar(int group) { u64 irqstat; - asm volatile("mrs_s %0, " xstr(ICC_IAR1_EL1) : "=r" (irqstat)); + + if (group == 0) + asm volatile("mrs_s %0, " xstr(ICC_IAR0_EL1) : "=r" (irqstat)); + else + asm volatile("mrs_s %0, " xstr(ICC_IAR1_EL1) : "=r" (irqstat)); + dsb(sy); return (u64)irqstat; }