diff mbox series

[1/2] arm64: Rename WORKAROUND_1165522 to SPECULATIVE_AT

Message ID 20191111141157.55062-2-steven.price@arm.com
State New, archived
Headers show
Series arm64: Workaround for Cortex-A55 erratum 1530923 | expand

Commit Message

Steven Price Nov. 11, 2019, 2:11 p.m. UTC
Cortex-A55 is affected by a similar erratum, so rename the existing
workaround for errarum 1165522 so it can be used for both errata.

Signed-off-by: Steven Price <steven.price@arm.com>
---
 arch/arm64/Kconfig                |  4 ++++
 arch/arm64/include/asm/cpucaps.h  |  2 +-
 arch/arm64/include/asm/kvm_host.h |  2 +-
 arch/arm64/include/asm/kvm_hyp.h  |  3 +--
 arch/arm64/kernel/cpu_errata.c    | 17 +++++++++++++----
 arch/arm64/kvm/hyp/switch.c       |  2 +-
 arch/arm64/kvm/hyp/tlb.c          |  4 ++--
 7 files changed, 23 insertions(+), 11 deletions(-)

Comments

Marc Zyngier Nov. 11, 2019, 3:42 p.m. UTC | #1
Hi Steven,

On 2019-11-11 15:21, Steven Price wrote:
> Cortex-A55 is affected by a similar erratum, so rename the existing
> workaround for errarum 1165522 so it can be used for both errata.

nit: erratum

>
> Signed-off-by: Steven Price <steven.price@arm.com>
> ---
>  arch/arm64/Kconfig                |  4 ++++
>  arch/arm64/include/asm/cpucaps.h  |  2 +-
>  arch/arm64/include/asm/kvm_host.h |  2 +-
>  arch/arm64/include/asm/kvm_hyp.h  |  3 +--
>  arch/arm64/kernel/cpu_errata.c    | 17 +++++++++++++----
>  arch/arm64/kvm/hyp/switch.c       |  2 +-
>  arch/arm64/kvm/hyp/tlb.c          |  4 ++--
>  7 files changed, 23 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 3f047afb982c..6cb4eff602c6 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -510,9 +510,13 @@ config ARM64_ERRATUM_1418040
>
>  	  If unsure, say Y.
>
> +config ARM64_WORKAROUND_SPECULATIVE_AT
> +	bool
> +
>  config ARM64_ERRATUM_1165522
>  	bool "Cortex-A76: Speculative AT instruction using out-of-context
> translation regime could cause subsequent request to generate an
> incorrect translation"
>  	default y
> +	select ARM64_WORKAROUND_SPECULATIVE_AT

I'd object that ARM64_ERRATUM_1319367 (and its big brother 1319537)
are also related to speculative AT execution, and yet are not covered
by this configuration symbol.

I can see three solutions to this:

- Either you call it SPECULATIVE_AT_VHE and introduce 
SPECULATIVE_AT_NVHE
   for symmetry

- Or you make SPECULATIVE_AT cover all the speculative AT errata, which
   may or may not work...

- Or even better, you just ammend the documentation to say that 1165522
   also covers the newly found A55 one (just like we have for A57/A72)

What do you think?

         M.
Steven Price Nov. 11, 2019, 4:07 p.m. UTC | #2
On 11/11/2019 15:42, Marc Zyngier wrote:
> Hi Steven,
> 
> On 2019-11-11 15:21, Steven Price wrote:
>> Cortex-A55 is affected by a similar erratum, so rename the existing
>> workaround for errarum 1165522 so it can be used for both errata.
> 
> nit: erratum

Thanks, I do seem to have trouble spelling it correctly :)

>>
>> Signed-off-by: Steven Price <steven.price@arm.com>
>> ---
>>  arch/arm64/Kconfig                |  4 ++++
>>  arch/arm64/include/asm/cpucaps.h  |  2 +-
>>  arch/arm64/include/asm/kvm_host.h |  2 +-
>>  arch/arm64/include/asm/kvm_hyp.h  |  3 +--
>>  arch/arm64/kernel/cpu_errata.c    | 17 +++++++++++++----
>>  arch/arm64/kvm/hyp/switch.c       |  2 +-
>>  arch/arm64/kvm/hyp/tlb.c          |  4 ++--
>>  7 files changed, 23 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
>> index 3f047afb982c..6cb4eff602c6 100644
>> --- a/arch/arm64/Kconfig
>> +++ b/arch/arm64/Kconfig
>> @@ -510,9 +510,13 @@ config ARM64_ERRATUM_1418040
>>
>>        If unsure, say Y.
>>
>> +config ARM64_WORKAROUND_SPECULATIVE_AT
>> +    bool
>> +
>>  config ARM64_ERRATUM_1165522
>>      bool "Cortex-A76: Speculative AT instruction using out-of-context
>> translation regime could cause subsequent request to generate an
>> incorrect translation"
>>      default y
>> +    select ARM64_WORKAROUND_SPECULATIVE_AT
> 
> I'd object that ARM64_ERRATUM_1319367 (and its big brother 1319537)
> are also related to speculative AT execution, and yet are not covered
> by this configuration symbol.

Good point.

> I can see three solutions to this:
> 
> - Either you call it SPECULATIVE_AT_VHE and introduce SPECULATIVE_AT_NVHE
>   for symmetry

Tempting...

> - Or you make SPECULATIVE_AT cover all the speculative AT errata, which
>   may or may not work...

This actually sounds the neatest, but I'm not sure whether there's going
to be any conflicts between VHE/NVHE. I'll prototype this and see how
ugly it is.

> - Or even better, you just ammend the documentation to say that 1165522
>   also covers the newly found A55 one (just like we have for A57/A72)

Well Mark Rutland disliked my initial thoughts about just including both
errata in one option like that - hence the refactoring in this patch.
Although of course that's exactly what's happened with 1319367/1319537...

> What do you think?

I'll have a go at SPECULATIVE_AT covering both VHE/NVHE - from an
initial look it seems like it should work and it would be neat if it
does. In particular it should avoid the necessity to require VHE when
the erratum is present.

Otherwise I guess SPECULATIVE_AT_{,N}VHE is probably second best.

Thanks,

Steve
Mark Rutland Nov. 11, 2019, 5:16 p.m. UTC | #3
On Mon, Nov 11, 2019 at 04:07:39PM +0000, Steven Price wrote:
> On 11/11/2019 15:42, Marc Zyngier wrote:
> >> +config ARM64_WORKAROUND_SPECULATIVE_AT
> >> +    bool
> >> +
> >>  config ARM64_ERRATUM_1165522
> >>      bool "Cortex-A76: Speculative AT instruction using out-of-context
> >> translation regime could cause subsequent request to generate an
> >> incorrect translation"
> >>      default y
> >> +    select ARM64_WORKAROUND_SPECULATIVE_AT
> > 
> > I'd object that ARM64_ERRATUM_1319367 (and its big brother 1319537)
> > are also related to speculative AT execution, and yet are not covered
> > by this configuration symbol.
> 
> Good point.
> 
> > I can see three solutions to this:
> > 
> > - Either you call it SPECULATIVE_AT_VHE and introduce SPECULATIVE_AT_NVHE
> >   for symmetry
> 
> Tempting...

FWIW, this sounds fine to me.

> > - Or you make SPECULATIVE_AT cover all the speculative AT errata, which
> >   may or may not work...
> 
> This actually sounds the neatest, but I'm not sure whether there's going
> to be any conflicts between VHE/NVHE. I'll prototype this and see how
> ugly it is.
> 
> > - Or even better, you just ammend the documentation to say that 1165522
> >   also covers the newly found A55 one (just like we have for A57/A72)
> 
> Well Mark Rutland disliked my initial thoughts about just including both
> errata in one option like that - hence the refactoring in this patch.
> Although of course that's exactly what's happened with 1319367/1319537...

My view on this is that using one erratum config symbol to cover the
workaround for another is more confusing than having a level of
indirection, and I would've preferred the indirection for that case too.
 
> > What do you think?
> 
> I'll have a go at SPECULATIVE_AT covering both VHE/NVHE - from an
> initial look it seems like it should work and it would be neat if it
> does. In particular it should avoid the necessity to require VHE when
> the erratum is present.
> 
> Otherwise I guess SPECULATIVE_AT_{,N}VHE is probably second best.

Both sound good to me.

Thanks for dealing with this!

Mark.
diff mbox series

Patch

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 3f047afb982c..6cb4eff602c6 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -510,9 +510,13 @@  config ARM64_ERRATUM_1418040
 
 	  If unsure, say Y.
 
+config ARM64_WORKAROUND_SPECULATIVE_AT
+	bool
+
 config ARM64_ERRATUM_1165522
 	bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 	default y
+	select ARM64_WORKAROUND_SPECULATIVE_AT
 	help
 	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
 
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index ac1dbca3d0cd..33c9545fe08a 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -44,7 +44,7 @@ 
 #define ARM64_SSBS				34
 #define ARM64_WORKAROUND_1418040		35
 #define ARM64_HAS_SB				36
-#define ARM64_WORKAROUND_1165522		37
+#define ARM64_WORKAROUND_SPECULATIVE_AT		37
 #define ARM64_HAS_ADDRESS_AUTH_ARCH		38
 #define ARM64_HAS_ADDRESS_AUTH_IMP_DEF		39
 #define ARM64_HAS_GENERIC_AUTH_ARCH		40
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index f656169db8c3..d9f35ef1675e 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -534,7 +534,7 @@  static inline bool kvm_arch_requires_vhe(void)
 		return true;
 
 	/* Some implementations have defects that confine them to VHE */
-	if (cpus_have_cap(ARM64_WORKAROUND_1165522))
+	if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_AT))
 		return true;
 
 	return false;
diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h
index 97f21cc66657..43d6c30b1bcc 100644
--- a/arch/arm64/include/asm/kvm_hyp.h
+++ b/arch/arm64/include/asm/kvm_hyp.h
@@ -95,8 +95,7 @@  static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm)
 	 * before we can switch to the EL1/EL0 translation regime used by
 	 * the guest.
 	 */
-	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_1165522));
-}
+	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); }
 
 #endif /* __ARM64_KVM_HYP_H__ */
 
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 93f34b4eca25..a9ea19fdaf03 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -772,6 +772,16 @@  static const struct arm64_cpu_capabilities erratum_843419_list[] = {
 };
 #endif
 
+#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
+static const struct midr_range erratum_speculative_at_list[] = {
+#ifdef CONFIG_ARM64_ERRATUM_1165522
+	/* Cortex A76 r0p0 to r2p0 */
+	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
+#endif
+	{},
+};
+#endif
+
 const struct arm64_cpu_capabilities arm64_errata[] = {
 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
 	{
@@ -898,12 +908,11 @@  const struct arm64_cpu_capabilities arm64_errata[] = {
 		ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
 	},
 #endif
-#ifdef CONFIG_ARM64_ERRATUM_1165522
+#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
 	{
-		/* Cortex-A76 r0p0 to r2p0 */
 		.desc = "ARM erratum 1165522",
-		.capability = ARM64_WORKAROUND_1165522,
-		ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
+		.capability = ARM64_WORKAROUND_SPECULATIVE_AT,
+		ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
 	},
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_1463225
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 799e84a40335..9b88627f9da9 100644
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -148,7 +148,7 @@  static void deactivate_traps_vhe(void)
 	 * before we can switch to the EL2/EL0 translation regime used by
 	 * the host.
 	 */
-	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_1165522));
+	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
 
 	write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
 	write_sysreg(vectors, vbar_el1);
diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c
index eb0efc5557f3..97e4b21367f1 100644
--- a/arch/arm64/kvm/hyp/tlb.c
+++ b/arch/arm64/kvm/hyp/tlb.c
@@ -23,7 +23,7 @@  static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm,
 
 	local_irq_save(cxt->flags);
 
-	if (cpus_have_const_cap(ARM64_WORKAROUND_1165522)) {
+	if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
 		/*
 		 * For CPUs that are affected by ARM erratum 1165522, we
 		 * cannot trust stage-1 to be in a correct state at that
@@ -87,7 +87,7 @@  static void __hyp_text __tlb_switch_to_host_vhe(struct kvm *kvm,
 	write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
 	isb();
 
-	if (cpus_have_const_cap(ARM64_WORKAROUND_1165522)) {
+	if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
 		/* Restore the registers to what they were */
 		write_sysreg_el1(cxt->tcr, SYS_TCR);
 		write_sysreg_el1(cxt->sctlr, SYS_SCTLR);