| Message ID | 20191115145915.6887-1-arnaud.pouliquen@st.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | dt-bindings: mailbox: convert stm32-ipcc to json-schema | expand |
On 11/15/19 3:59 PM, Arnaud Pouliquen wrote: > Convert the STM32 IPCC bindings to DT schema format using > json-schema > > Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> > --- > .../bindings/mailbox/st,stm32-ipcc.yaml | 91 +++++++++++++++++++ > .../bindings/mailbox/stm32-ipcc.txt | 47 ---------- > 2 files changed, 91 insertions(+), 47 deletions(-) > create mode 100644 Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml > delete mode 100644 Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt > > diff --git a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml > new file mode 100644 > index 000000000000..6843d51d96da > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: STM32 GPIO and Pin Mux/Config controller oops stupid copy/past, V2 coming soon > + > +description: | > + The IPCC block provides a non blocking signaling mechanism to post and > + retrieve messages in an atomic way between two processors. > + It provides the signaling for N bidirectionnal channels. The number of > + channels (N) can be read from a dedicated register. > + > +maintainers: > + - Fabien Dessenne <fabien.dessenne@st.com> > + - Arnaud Pouliquen <arnaud.pouliquen@st.com> > + > +properties: > + compatible: > + const: st,stm32mp1-ipcc > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + interrupts: > + items: > + - description: rx channel occupied > + - description: tx channel free > + - description: wakeup source > + minItems: 2 > + maxItems: 3 > + > + interrupt-names: > + items: > + enums: [ rx, tx, wakeup ] > + minItems: 2 > + maxItems: 3 > + > + wakeup-source: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Enables wake up of host system on wakeup IRQ assertion. > + > + "#mbox-cells": > + const: 1 > + > + st,proc-id: > + description: Processor id using the mailbox (0 or 1) > + allOf: > + - minimum: 0 > + - maximum: 1 > + - default: 0 > + > +required: > + - compatible > + - reg > + - st,proc-id > + - clocks > + - interrupt-names > + - "#mbox-cells" > + > +oneOf: > + - required: > + - interrupts > + - required: > + - interrupts-extended > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/stm32mp1-clks.h> > + ipcc: mailbox@4c001000 { > + compatible = "st,stm32mp1-ipcc"; > + #mbox-cells = <1>; > + reg = <0x4c001000 0x400>; > + st,proc-id = <0>; > + interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, > + <&intc GIC_SPI 101 IRQ_TYPE_NONE>, > + <&aiec 62 1>; > + interrupt-names = "rx", "tx", "wakeup"; > + clocks = <&rcc_clk IPCC>; > + wakeup-source; > + }; > + > +... > diff --git a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt b/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt > deleted file mode 100644 > index 1d2b7fee7b85..000000000000 > --- a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt > +++ /dev/null > @@ -1,47 +0,0 @@ > -* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller) > - > -The IPCC block provides a non blocking signaling mechanism to post and > -retrieve messages in an atomic way between two processors. > -It provides the signaling for N bidirectionnal channels. The number of channels > -(N) can be read from a dedicated register. > - > -Required properties: > -- compatible: Must be "st,stm32mp1-ipcc" > -- reg: Register address range (base address and length) > -- st,proc-id: Processor id using the mailbox (0 or 1) > -- clocks: Input clock > -- interrupt-names: List of names for the interrupts described by the interrupt > - property. Must contain the following entries: > - - "rx" > - - "tx" > - - "wakeup" > -- interrupts: Interrupt specifiers for "rx channel occupied", "tx channel > - free" and "system wakeup". > -- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1. > - The data contained in the mbox specifier of the "mboxes" > - property in the client node is the mailbox channel index. > - > -Optional properties: > -- wakeup-source: Flag to indicate whether this device can wake up the system > - > - > - > -Example: > - ipcc: mailbox@4c001000 { > - compatible = "st,stm32mp1-ipcc"; > - #mbox-cells = <1>; > - reg = <0x4c001000 0x400>; > - st,proc-id = <0>; > - interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, > - <&intc GIC_SPI 101 IRQ_TYPE_NONE>, > - <&aiec 62 1>; > - interrupt-names = "rx", "tx", "wakeup"; > - clocks = <&rcc_clk IPCC>; > - wakeup-source; > - } > - > -Client: > - mbox_test { > - ... > - mboxes = <&ipcc 0>, <&ipcc 1>; > - };
diff --git a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml new file mode 100644 index 000000000000..6843d51d96da --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STM32 GPIO and Pin Mux/Config controller + +description: | + The IPCC block provides a non blocking signaling mechanism to post and + retrieve messages in an atomic way between two processors. + It provides the signaling for N bidirectionnal channels. The number of + channels (N) can be read from a dedicated register. + +maintainers: + - Fabien Dessenne <fabien.dessenne@st.com> + - Arnaud Pouliquen <arnaud.pouliquen@st.com> + +properties: + compatible: + const: st,stm32mp1-ipcc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + items: + - description: rx channel occupied + - description: tx channel free + - description: wakeup source + minItems: 2 + maxItems: 3 + + interrupt-names: + items: + enums: [ rx, tx, wakeup ] + minItems: 2 + maxItems: 3 + + wakeup-source: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enables wake up of host system on wakeup IRQ assertion. + + "#mbox-cells": + const: 1 + + st,proc-id: + description: Processor id using the mailbox (0 or 1) + allOf: + - minimum: 0 + - maximum: 1 + - default: 0 + +required: + - compatible + - reg + - st,proc-id + - clocks + - interrupt-names + - "#mbox-cells" + +oneOf: + - required: + - interrupts + - required: + - interrupts-extended + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + ipcc: mailbox@4c001000 { + compatible = "st,stm32mp1-ipcc"; + #mbox-cells = <1>; + reg = <0x4c001000 0x400>; + st,proc-id = <0>; + interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, + <&intc GIC_SPI 101 IRQ_TYPE_NONE>, + <&aiec 62 1>; + interrupt-names = "rx", "tx", "wakeup"; + clocks = <&rcc_clk IPCC>; + wakeup-source; + }; + +... diff --git a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt b/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt deleted file mode 100644 index 1d2b7fee7b85..000000000000 --- a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt +++ /dev/null @@ -1,47 +0,0 @@ -* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller) - -The IPCC block provides a non blocking signaling mechanism to post and -retrieve messages in an atomic way between two processors. -It provides the signaling for N bidirectionnal channels. The number of channels -(N) can be read from a dedicated register. - -Required properties: -- compatible: Must be "st,stm32mp1-ipcc" -- reg: Register address range (base address and length) -- st,proc-id: Processor id using the mailbox (0 or 1) -- clocks: Input clock -- interrupt-names: List of names for the interrupts described by the interrupt - property. Must contain the following entries: - - "rx" - - "tx" - - "wakeup" -- interrupts: Interrupt specifiers for "rx channel occupied", "tx channel - free" and "system wakeup". -- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1. - The data contained in the mbox specifier of the "mboxes" - property in the client node is the mailbox channel index. - -Optional properties: -- wakeup-source: Flag to indicate whether this device can wake up the system - - - -Example: - ipcc: mailbox@4c001000 { - compatible = "st,stm32mp1-ipcc"; - #mbox-cells = <1>; - reg = <0x4c001000 0x400>; - st,proc-id = <0>; - interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, - <&intc GIC_SPI 101 IRQ_TYPE_NONE>, - <&aiec 62 1>; - interrupt-names = "rx", "tx", "wakeup"; - clocks = <&rcc_clk IPCC>; - wakeup-source; - } - -Client: - mbox_test { - ... - mboxes = <&ipcc 0>, <&ipcc 1>; - };
Convert the STM32 IPCC bindings to DT schema format using json-schema Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> --- .../bindings/mailbox/st,stm32-ipcc.yaml | 91 +++++++++++++++++++ .../bindings/mailbox/stm32-ipcc.txt | 47 ---------- 2 files changed, 91 insertions(+), 47 deletions(-) create mode 100644 Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml delete mode 100644 Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt