From patchwork Thu Nov 21 05:02:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 11255295 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4AE1B14C0 for ; Thu, 21 Nov 2019 05:03:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C929E20672 for ; Thu, 21 Nov 2019 05:03:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="JTBe9fRJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C929E20672 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zsu2w1VN5HANjOJcMHWUyctbEn+TnojwabdJXyPhf9Q=; b=JTBe9fRJZgEt6N vRDJAUzfBkPFHaOCzKnpvPK+n+LqHqOZj0B7eTrLzy/34YHEICsC7f43XUA2JruyLGlXQGHjKCG1H R5PvxHevuGsbyLR2n2GPglGB0zhZwgWE0ig1zQRLybEoS3cQEHrh56Kt93v3LLJySjYtAsfB4iS0T 9lpGqArWPyLu/LDckp90j8aiwAH/gIqQaPq6zId/rZgNKZXuLLXPPo0ehbB6LO6AlG044h+Y2FEEK zDuJ7IkozHCAz67bhfxm9+qeTCOxQfaxpksHxFhb9zxZAiBVjmCYPi2EnPHojkFhRqy6ccoTuSAiT SX/h3GObSBfkSFHQa1bA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXed3-0005Eh-KS; Thu, 21 Nov 2019 05:03:41 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXebp-00046Z-7c; Thu, 21 Nov 2019 05:02:28 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 5B27CB15E; Thu, 21 Nov 2019 05:02:21 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Subject: [PATCH v5 8/9] irqchip: rtd1195-mux: Add RTD1395 definitions Date: Thu, 21 Nov 2019 06:02:07 +0100 Message-Id: <20191121050208.11324-9-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191120_210225_587563_452AD323 X-CRM114-Status: GOOD ( 10.85 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Thomas Gleixner , =?utf-8?q?Andreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add compatible strings and bit mappings for Realtek RTD1395 SoC. Based on BPI-M4-bsp linux-rtk/drivers/irqchip/irq-rtd139x.h. Signed-off-by: Andreas Färber --- @Realtek: Does RTD1395 still have the WDOG_NMI misc interrupt at bit 2? v4 -> v5: * Renamed misc bits from MISC_ to MIS_ for consistency * Filled in irq_chip names v4: New drivers/irqchip/irq-rtd1195-mux.c | 85 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c index e3e2e42d9df2..e0264759c0a8 100644 --- a/drivers/irqchip/irq-rtd1195-mux.c +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Realtek RTD1195/RTD1295 IRQ mux + * Realtek RTD1195/RTD1295/RTD1395 IRQ mux * + * Copyright (C) 2017 Realtek Semiconductor Corporation * Copyright (c) 2017-2019 Andreas Färber */ @@ -314,6 +315,62 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { [RTD1295_MIS_ISR_WDOG_NMI_SHIFT] = SCPU_INT_EN_NMI_MASK, }; +enum rtd1395_iso_isr_bits { + RTD1395_ISO_ISR_UR0_SHIFT = 2, + RTD1395_ISO_ISR_IRDA_SHIFT = 5, + RTD1395_ISO_ISR_I2C0_SHIFT = 8, + RTD1395_ISO_ISR_I2C1_SHIFT = 11, + RTD1395_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1395_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1395_ISO_ISR_LSADC0_SHIFT = 16, + RTD1395_ISO_ISR_LSADC1_SHIFT = 17, + RTD1395_ISO_ISR_GPIOA_SHIFT = 19, + RTD1395_ISO_ISR_GPIODA_SHIFT = 20, + RTD1395_ISO_ISR_GPHY_HV_SHIFT = 28, + RTD1395_ISO_ISR_GPHY_DV_SHIFT = 29, + RTD1395_ISO_ISR_GPHY_AV_SHIFT = 30, + RTD1395_ISO_ISR_I2C1_REQ_SHIFT = 31, +}; + +static const u32 rtd1395_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1395_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1395_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1395_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1395_ISO_ISR_I2C1_SHIFT] = BIT(11), + [RTD1395_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1395_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1395_ISO_ISR_LSADC0_SHIFT] = BIT(16), + [RTD1395_ISO_ISR_LSADC1_SHIFT] = BIT(17), + [RTD1395_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1395_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1395_ISO_ISR_GPHY_HV_SHIFT] = BIT(28), + [RTD1395_ISO_ISR_GPHY_DV_SHIFT] = BIT(29), + [RTD1395_ISO_ISR_GPHY_AV_SHIFT] = BIT(30), + [RTD1395_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31), +}; + +enum rtd1395_misc_isr_bits { + RTD1395_MIS_ISR_UR1_SHIFT = 3, + RTD1395_MIS_ISR_UR1_TO_SHIFT = 5, + RTD1395_MIS_ISR_UR2_SHIFT = 8, + RTD1395_MIS_ISR_UR2_TO_SHIFT = 13, + RTD1395_MIS_ISR_I2C5_SHIFT = 14, + RTD1395_MIS_ISR_SC0_SHIFT = 24, + RTD1395_MIS_ISR_SPI_SHIFT = 27, + RTD1395_MIS_ISR_FAN_SHIFT = 29, +}; + +static const u32 rtd1395_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1395_MIS_ISR_UR1_SHIFT] = BIT(3), + [RTD1395_MIS_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1395_MIS_ISR_UR2_TO_SHIFT] = BIT(6), + [RTD1395_MIS_ISR_UR2_SHIFT] = BIT(7), + [RTD1395_MIS_ISR_I2C5_SHIFT] = BIT(14), + [RTD1395_MIS_ISR_SC0_SHIFT] = BIT(24), + [RTD1395_MIS_ISR_SPI_SHIFT] = BIT(27), + [RTD1395_MIS_ISR_FAN_SHIFT] = BIT(29), +}; + static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = { .name = "iso", .isr_offset = 0x0, @@ -330,6 +387,14 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1395_iso_irq_mux_info = { + .name = "iso", + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1395_iso_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = { .name = "misc", .umsk_isr_offset = 0x8, @@ -346,6 +411,14 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { .isr_to_int_en_mask = rtd1295_misc_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1395_misc_irq_mux_info = { + .name = "misc", + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1395_misc_isr_to_scpu_int_en_mask, +}; + static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { { .compatible = "realtek,rtd1195-iso-irq-mux", @@ -355,6 +428,10 @@ static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { .compatible = "realtek,rtd1295-iso-irq-mux", .data = &rtd1295_iso_irq_mux_info, }, + { + .compatible = "realtek,rtd1395-iso-irq-mux", + .data = &rtd1395_iso_irq_mux_info, + }, { .compatible = "realtek,rtd1195-misc-irq-mux", .data = &rtd1195_misc_irq_mux_info, @@ -363,6 +440,10 @@ static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { .compatible = "realtek,rtd1295-misc-irq-mux", .data = &rtd1295_misc_irq_mux_info, }, + { + .compatible = "realtek,rtd1395-misc-irq-mux", + .data = &rtd1395_misc_irq_mux_info, + }, { } }; @@ -425,5 +506,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node, } IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1395_iso_mux, "realtek,rtd1395-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1395_misc_mux, "realtek,rtd1395-misc-irq-mux", rtd1195_irq_mux_init);