| Message ID | 20191129234108.12732-2-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] soc: imx: gpcv2: Add support for imx8mm | expand |
Hi Adam, On Fri, Nov 29, 2019 at 8:41 PM Adam Ford <aford173@gmail.com> wrote: > + > + gpc: gpc@303a0000 { > + compatible = "fsl,imx8mm-gpc"; You could do like this instead: compatible = "fsl,imx8mm-gpc", "fsl,imx8mq-gpc"; and then you don't need patch 1/2. Also, "fsl,imx8mm-gpc" needs to be documented.
On Sat, Nov 30, 2019 at 7:25 PM Fabio Estevam <festevam@gmail.com> wrote: > > Hi Adam, > > On Fri, Nov 29, 2019 at 8:41 PM Adam Ford <aford173@gmail.com> wrote: > > > + > > + gpc: gpc@303a0000 { > > + compatible = "fsl,imx8mm-gpc"; > > You could do like this instead: > > compatible = "fsl,imx8mm-gpc", "fsl,imx8mq-gpc"; > > and then you don't need patch 1/2. > > Also, "fsl,imx8mm-gpc" needs to be documented. One more thing: when you add a v2, please specify the SoC name in the subject line: arm64: dts: imx8mm: Add GPC Support
On Sat, Nov 30, 2019 at 4:30 PM Fabio Estevam <festevam@gmail.com> wrote: > > On Sat, Nov 30, 2019 at 7:25 PM Fabio Estevam <festevam@gmail.com> wrote: > > > > Hi Adam, > > > > On Fri, Nov 29, 2019 at 8:41 PM Adam Ford <aford173@gmail.com> wrote: > > > > > + > > > + gpc: gpc@303a0000 { > > > + compatible = "fsl,imx8mm-gpc"; > > > > You could do like this instead: > > > > compatible = "fsl,imx8mm-gpc", "fsl,imx8mq-gpc"; > > > > and then you don't need patch 1/2. I like that idea. > > > > Also, "fsl,imx8mm-gpc" needs to be documented. I held off intentionally because of all the txt->yaml conversion, I didn't want to get stuck in the middle of that. Would an tweak to the txt file be accepted? If not, should I just use the "fsl,imx8mq-gpc" and leave it alone? > > One more thing: when you add a v2, please specify the SoC name in the > subject line: > > arm64: dts: imx8mm: Add GPC Support Good catch. Sorry about that. adam
On Sat, Nov 30, 2019 at 7:50 PM Adam Ford <aford173@gmail.com> wrote: > I held off intentionally because of all the txt->yaml conversion, I > didn't want to get stuck in the middle of that. > > Would an tweak to the txt file be accepted? Yes, a patch to the existing txt binding should be fine.
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 6edbdfe2d0d7..860cddec9632 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/imx8mm-clock.h> +#include <dt-bindings/power/imx8mq-power.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -498,6 +499,90 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mm-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_mipi: power-domain@0 { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_MIPI>; + }; + + /* + * As per comment in ATF source code: + * + * PCIE1 and PCIE2 share the + * same reset signal, if we + * power down PCIE2, PCIE1 + * will be held in reset too. + * + * So instead of creating two + * separate power domains for + * PCIE1 and PCIE2 we create a + * link between both and use + * it as a shared PCIE power + * domain. + */ + pgc_pcie: power-domain@1 { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_PCIE1>; + power-domains = <&pgc_pcie2>; + }; + + pgc_otg1: power-domain@2 { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; + }; + + pgc_otg2: power-domain@3 { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; + }; + + pgc_ddr1: power-domain@4 { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_DDR1>; + }; + + pgc_gpu: power-domain@5 { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_GPU>; + }; + + pgc_vpu: power-domain@6 { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_VPU>; + }; + + pgc_disp: power-domain@7 { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_DISP>; + }; + + pgc_mipi_csi1: power-domain@8 { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; + }; + + pgc_mipi_csi2: power-domain@9 { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; + }; + + pgc_pcie2: power-domain@a { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_PCIE2>; + }; + }; + }; }; aips2: bus@30400000 {
The General Power Controller (GPC) used on the i.MX8MQ is the same as what is used on the i.MX8M Mini. This patch adds the GPC support to the device tree for the SoC. Signed-off-by: Adam Ford <aford173@gmail.com>