From patchwork Thu Jan 2 12:39:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11315669 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ABF15109A for ; Thu, 2 Jan 2020 12:39:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 83F9B20863 for ; Thu, 2 Jan 2020 12:39:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Ou9mBOQo" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 83F9B20863 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hxBfFhgQ+bb/5aGRu+tJslvX3Y6ILZe+73o8FyZb4DM=; b=Ou9mBOQomAdah/ y7Pjp1EXOwOFPGWOw+5nkZQlrV7fngZM3oIUHhEu/EXpeWXBbwvhTQ5dv1SYvM3N6siBiCU+dSelB fzAuvCEqkZ8tgv7Ed9r6G/96foarlGJoV8hAQvob3teMyiPDAa7lDDCyZPKWnVjOtZDs0wPFsi5Hf yPOdaE1ZJViyvc2G8VaU9l9TYQfce02w8KQpq4RWgW2shjMFtguhCmj+74gKQK85PZvhnmGRqdqyX 7d+e6K9ZEplZ7WD70YhbZdUvSpvZ8hliWcPBRXE3NnF42RyQuhmFm8xv007sjuuBBmEa4MeNMzQ1R KNX3iLoBV8l4M0k0t7Vw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1imzlJ-0005xB-QC; Thu, 02 Jan 2020 12:39:37 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1imzkz-0005Ys-Jr for linux-arm-kernel@lists.infradead.org; Thu, 02 Jan 2020 12:39:19 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 183431007; Thu, 2 Jan 2020 04:39:16 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 914B33F703; Thu, 2 Jan 2020 04:39:14 -0800 (PST) From: Andrew Murray To: Catalin Marinas , Will Deacon , Marc Zyngier , Mark Rutland Subject: [PATCH v3 2/3] KVM: arm64: limit PMU version to ARMv8.4 Date: Thu, 2 Jan 2020 12:39:04 +0000 Message-Id: <20200102123905.29360-3-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200102123905.29360-1-andrew.murray@arm.com> References: <20200102123905.29360-1-andrew.murray@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200102_043917_734494_CFCDC989 X-CRM114-Status: GOOD ( 12.20 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Suzuki Kuruppassery Poulose Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org ARMv8.5-PMU introduces 64-bit event counters, however KVM doesn't yet support this. Let's trap the Debug Feature Registers in order to limit PMUVer/PerfMon in the Debug Feature Registers to PMUv3 for ARMv8.4. Signed-off-by: Andrew Murray Reviewed-by: Suzuki K Poulose --- arch/arm64/include/asm/sysreg.h | 4 ++++ arch/arm64/kvm/sys_regs.c | 36 +++++++++++++++++++++++++++++++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6e919fafb43d..1b74f275a115 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -672,6 +672,10 @@ #define ID_AA64DFR0_TRACEVER_SHIFT 4 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 +#define ID_DFR0_PERFMON_SHIFT 24 + +#define ID_DFR0_EL1_PMUVER_8_4 5 + #define ID_ISAR5_RDM_SHIFT 24 #define ID_ISAR5_CRC32_SHIFT 16 #define ID_ISAR5_SHA2_SHIFT 12 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 9f2165937f7d..61b984d934d1 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -668,6 +668,37 @@ static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); } +static bool access_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *rd) +{ + if (p->is_write) + return write_to_read_only(vcpu, p, rd); + + /* Limit guests to PMUv3 for ARMv8.4 */ + p->regval = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + p->regval = cpuid_feature_cap_signed_field_width(p->regval, + ID_AA64DFR0_PMUVER_SHIFT, + 4, ID_DFR0_EL1_PMUVER_8_4); + + return p->regval; +} + +static bool access_id_dfr0_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, + const struct sys_reg_desc *rd) +{ + if (p->is_write) + return write_to_read_only(vcpu, p, rd); + + /* Limit guests to PMUv3 for ARMv8.4 */ + p->regval = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); + p->regval = cpuid_feature_cap_signed_field_width(p->regval, + ID_DFR0_PERFMON_SHIFT, + 4, ID_DFR0_EL1_PMUVER_8_4); + + return p->regval; +} + static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { @@ -1409,7 +1440,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* CRm=1 */ ID_SANITISED(ID_PFR0_EL1), ID_SANITISED(ID_PFR1_EL1), - ID_SANITISED(ID_DFR0_EL1), + { SYS_DESC(SYS_ID_DFR0_EL1), access_id_dfr0_el1 }, + ID_HIDDEN(ID_AFR0_EL1), ID_SANITISED(ID_MMFR0_EL1), ID_SANITISED(ID_MMFR1_EL1), @@ -1448,7 +1480,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(4,7), /* CRm=5 */ - ID_SANITISED(ID_AA64DFR0_EL1), + { SYS_DESC(SYS_ID_AA64DFR0_EL1), access_id_aa64dfr0_el1 }, ID_SANITISED(ID_AA64DFR1_EL1), ID_UNALLOCATED(5,2), ID_UNALLOCATED(5,3),