| Message ID | 20200109085152.10573-1-faiz_abbas@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm: dts: ti: k3-am654-main: Update otap-del-sel values | expand |
On 09/01/2020 10:51, Faiz Abbas wrote: > According to the latest AM65x Data Manual[1], a different output tap > delay value is optimum for a given speed mode. Update these values. > > [1] http://www.ti.com/lit/gpn/am6526 > > Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> I believe this patch is going to be updated, as the dt binding has received comments. As such, going to ignore this for now. -Tero > --- > > This patch depends on my two kernel series posted here: > https://patchwork.kernel.org/project/linux-mmc/list/?series=225425 > https://patchwork.kernel.org/project/linux-mmc/list/?series=225459 > > arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > index efb24579922c..c8d812fdfa0a 100644 > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > @@ -253,7 +253,17 @@ > interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; > mmc-ddr-1_8v; > mmc-hs200-1_8v; > - ti,otap-del-sel = <0x2>; > + ti,otap-del-sel-legacy = <0x0>; > + ti,otap-del-sel-mmc-hs = <0x0>; > + ti,otap-del-sel-sd-hs = <0x0>; > + ti,otap-del-sel-sdr12 = <0x0>; > + ti,otap-del-sel-sdr25 = <0x0>; > + ti,otap-del-sel-sdr50 = <0x8>; > + ti,otap-del-sel-sdr104 = <0x5>; > + ti,otap-del-sel-ddr50 = <0x5>; > + ti,otap-del-sel-ddr52 = <0x5>; > + ti,otap-del-sel-hs200 = <0x5>; > + ti,otap-del-sel-hs400 = <0x0>; > ti,trm-icp = <0x8>; > dma-coherent; > }; > -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Tero, On 17/01/20 1:38 pm, Tero Kristo wrote: > On 09/01/2020 10:51, Faiz Abbas wrote: >> According to the latest AM65x Data Manual[1], a different output tap >> delay value is optimum for a given speed mode. Update these values. >> >> [1] http://www.ti.com/lit/gpn/am6526 >> >> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> > > I believe this patch is going to be updated, as the dt binding has > received comments. As such, going to ignore this for now. > Those other series are merged now so you should be able to pick this up. Thanks, Faiz
On 09/03/2020 09:11, Faiz Abbas wrote: > Tero, > > On 17/01/20 1:38 pm, Tero Kristo wrote: >> On 09/01/2020 10:51, Faiz Abbas wrote: >>> According to the latest AM65x Data Manual[1], a different output tap >>> delay value is optimum for a given speed mode. Update these values. >>> >>> [1] http://www.ti.com/lit/gpn/am6526 >>> >>> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> >> >> I believe this patch is going to be updated, as the dt binding has >> received comments. As such, going to ignore this for now. >> > > Those other series are merged now so you should be able to pick this up. There were no changes to the DT binding? Can you resend the DTS patch, and refer to the merged dt-binding? I deleted the whole series from my inbox already based on above. -Tero -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index efb24579922c..c8d812fdfa0a 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -253,7 +253,17 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-sdr104 = <0x5>; + ti,otap-del-sel-ddr50 = <0x5>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x5>; + ti,otap-del-sel-hs400 = <0x0>; ti,trm-icp = <0x8>; dma-coherent; };
According to the latest AM65x Data Manual[1], a different output tap delay value is optimum for a given speed mode. Update these values. [1] http://www.ti.com/lit/gpn/am6526 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> --- This patch depends on my two kernel series posted here: https://patchwork.kernel.org/project/linux-mmc/list/?series=225425 https://patchwork.kernel.org/project/linux-mmc/list/?series=225459 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)