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[81.140.166.164]) by smtp.gmail.com with ESMTPSA id e18sm8643101wrr.95.2020.01.09.08.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 08:06:19 -0800 (PST) From: Julien Thierry To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC v5 25/57] objtool: arm64: Decode calls to higher EL Date: Thu, 9 Jan 2020 16:02:28 +0000 Message-Id: <20200109160300.26150-26-jthierry@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200109160300.26150-1-jthierry@redhat.com> References: <20200109160300.26150-1-jthierry@redhat.com> MIME-Version: 1.0 X-MC-Unique: XT7vV1PiNzK6TgT5WZy-PQ-1 X-Mimecast-Spam-Score: 0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200109_080624_412875_5D03DCEF X-CRM114-Status: GOOD ( 11.72 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [205.139.110.61 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julien Thierry , peterz@infradead.org, catalin.marinas@arm.com, raphael.gault@arm.com, jpoimboe@redhat.com, will@kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Decode instructions that volontarily trigger exceptions to a higher exception level. It is assumed that the higher exception level should service the request in a sane maner, returning to the caller exception level without altering its context too much (e.g. not modifying the PC, the stack pointer or the frame pointer). Suggested-by: Raphael Gault Signed-off-by: Julien Thierry --- tools/objtool/arch/arm64/decode.c | 45 +++++++++++++++++++ .../objtool/arch/arm64/include/insn_decode.h | 2 + 2 files changed, 47 insertions(+) diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c index c38d73fb57e1..aa00de725686 100644 --- a/tools/objtool/arch/arm64/decode.c +++ b/tools/objtool/arch/arm64/decode.c @@ -419,6 +419,11 @@ static struct aarch64_insn_decoder br_sys_decoder[] = { .value = 0b1100100010000000000000, .decode_func = arm_decode_system_regs, }, + { + .mask = 0b1111100000000000000000, + .value = 0b1100000000000000000000, + .decode_func = arm_decode_except_gen, + }, }; int arm_decode_br_sys(u32 instr, enum insn_type *type, @@ -486,3 +491,43 @@ int arm_decode_system_regs(u32 instr, enum insn_type *type, *type = INSN_OTHER; return 0; } + +int arm_decode_except_gen(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + u32 imm16 = 0; + unsigned char opc = 0, op2 = 0, LL = 0, decode_field = 0; + + imm16 = (instr >> 5) & ONES(16); + opc = (instr >> 21) & ONES(3); + op2 = (instr >> 2) & ONES(3); + LL = instr & ONES(2); + decode_field = (opc << 5) | (op2 << 2) | LL; + +#define INSN_SVC 0b00000001 +#define INSN_HVC 0b00000010 +#define INSN_SMC 0b00000011 + + switch (decode_field) { + case INSN_SVC: + case INSN_HVC: + case INSN_SMC: + /* + * We consider that the context will be restored correctly + * with an unchanged sp and the same general registers + */ + *type = INSN_NOP; + return 0; + default: + return arm_decode_unknown(instr, type, immediate, ops_list); + } + +#undef INSN_SVC +#undef INSN_HVC +#undef INSN_SMC +#undef INSN_BRK +#undef INSN_HLT +#undef INSN_DCPS1 +#undef INSN_DCPS2 +#undef INSN_DCPS3 +} diff --git a/tools/objtool/arch/arm64/include/insn_decode.h b/tools/objtool/arch/arm64/include/insn_decode.h index 777a62f1a141..a55dcbfcfed2 100644 --- a/tools/objtool/arch/arm64/include/insn_decode.h +++ b/tools/objtool/arch/arm64/include/insn_decode.h @@ -70,4 +70,6 @@ int arm_decode_system_insn(u32 instr, enum insn_type *type, int arm_decode_system_regs(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list); +int arm_decode_except_gen(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list); #endif /* _ARM_INSN_DECODE_H */