| Message ID | 20200219180858.4806-2-andrey.lebedev@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/5] drm/sun4i: tcon: Introduce LVDS setup routine setting | expand |
On Wed, Feb 19, 2020 at 08:08:54PM +0200, Andrey Lebedev wrote: > From: Andrey Lebedev <andrey@lebedev.lt> > > Different sunxi flavors require slightly different sequence for enabling > LVDS output. This allows to differentiate between them. > > Signed-off-by: Andrey Lebedev <andrey@lebedev.lt> > --- > drivers/gpu/drm/sun4i/sun4i_tcon.c | 68 ++++++++++++++++-------------- > drivers/gpu/drm/sun4i/sun4i_tcon.h | 3 ++ > 2 files changed, 39 insertions(+), 32 deletions(-) > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c > index c81cdce6ed55..cc6b05ca2c69 100644 > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > @@ -114,46 +114,48 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, > } > } > > +static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, > + const struct drm_encoder *encoder) > +{ > + u8 val; > + > + regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, > + SUN6I_TCON0_LVDS_ANA0_C(2) | > + SUN6I_TCON0_LVDS_ANA0_V(3) | > + SUN6I_TCON0_LVDS_ANA0_PD(2) | > + SUN6I_TCON0_LVDS_ANA0_EN_LDO); > + udelay(2); > + > + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, > + SUN6I_TCON0_LVDS_ANA0_EN_MB, > + SUN6I_TCON0_LVDS_ANA0_EN_MB); > + udelay(2); > + > + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, > + SUN6I_TCON0_LVDS_ANA0_EN_DRVC, > + SUN6I_TCON0_LVDS_ANA0_EN_DRVC); > + > + if (sun4i_tcon_get_pixel_depth(encoder) == 18) > + val = 7; > + else > + val = 0xf; > + > + regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, > + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), > + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); > + > +} > + There's an extra blank line here that was reported by checkpatch. I've fixed it up while applying. Maxime
On 2/20/20 7:21 PM, Maxime Ripard wrote: >> + regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, >> + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), >> + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); >> + >> +} >> + > There's an extra blank line here that was reported by checkpatch. I've > fixed it up while applying. Weird, checkpatch didn't warn me about that: ./scripts/checkpatch.pl patches/0001-drm-sun4i-tcon-Introduce-LVDS-setup-routine-setting.patch total: 0 errors, 0 warnings, 103 lines checked patches/0001-drm-sun4i-tcon-Introduce-LVDS-setup-routine-setting.patch has no obvious style problems and is ready for submission. In any case, thanks for correcting it!
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index c81cdce6ed55..cc6b05ca2c69 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -114,46 +114,48 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, } } +static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder) +{ + u8 val; + + regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_C(2) | + SUN6I_TCON0_LVDS_ANA0_V(3) | + SUN6I_TCON0_LVDS_ANA0_PD(2) | + SUN6I_TCON0_LVDS_ANA0_EN_LDO); + udelay(2); + + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_MB, + SUN6I_TCON0_LVDS_ANA0_EN_MB); + udelay(2); + + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_DRVC, + SUN6I_TCON0_LVDS_ANA0_EN_DRVC); + + if (sun4i_tcon_get_pixel_depth(encoder) == 18) + val = 7; + else + val = 0xf; + + regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); + +} + static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, const struct drm_encoder *encoder, bool enabled) { if (enabled) { - u8 val; - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, SUN4I_TCON0_LVDS_IF_EN); - - /* - * As their name suggest, these values only apply to the A31 - * and later SoCs. We'll have to rework this when merging - * support for the older SoCs. - */ - regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_C(2) | - SUN6I_TCON0_LVDS_ANA0_V(3) | - SUN6I_TCON0_LVDS_ANA0_PD(2) | - SUN6I_TCON0_LVDS_ANA0_EN_LDO); - udelay(2); - - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_MB, - SUN6I_TCON0_LVDS_ANA0_EN_MB); - udelay(2); - - regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_DRVC, - SUN6I_TCON0_LVDS_ANA0_EN_DRVC); - - if (sun4i_tcon_get_pixel_depth(encoder) == 18) - val = 7; - else - val = 0xf; - - regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, - SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), - SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); + if (tcon->quirks->setup_lvds_phy) + tcon->quirks->setup_lvds_phy(tcon, encoder); } else { regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, 0); @@ -1465,12 +1467,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = { .has_channel_0 = true, .has_lvds_alt = true, .dclk_min_div = 1, + .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, }; static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = { .supports_lvds = true, .has_channel_0 = true, .dclk_min_div = 1, + .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, }; static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index a62ec826ae71..2974e59ef9f2 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -228,6 +228,9 @@ struct sun4i_tcon_quirks { /* callback to handle tcon muxing options */ int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *); + /* handler for LVDS setup routine */ + void (*setup_lvds_phy)(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder); }; struct sun4i_tcon {