[2/3] arm64: insn: Add constants for PAC and BTI instruction decode

Commit Message

Mark Brown March 24, 2020, 7:48 p.m. UTC

Add constants for decoding the various PAC and BTI instructions defined
in the HINT space. Since we are now decoding both the op2 and CRm fields
rename the enum as well; this is compatible with what the existing users
are doing.

Signed-off-by: Mark Brown <[e-mail]>
---
 arch/arm64/include/asm/insn.h | 22 ++++++++++++++++++++--
 arch/arm64/kernel/insn.c      |  2 +-
 2 files changed, 21 insertions(+), 3 deletions(-)

Comments

Mark Brown April 28, 2020, 11:43 a.m. UTC | #1

On Tue, Mar 24, 2020 at 07:48:21PM +0000, Mark Brown wrote:

> +	AARCH64_INSN_HINT_BTI   = 0x40 << 5,
> +	AARCH64_INSN_HINT_BTIC  = 0x42 << 5,
> +	AARCH64_INSN_HINT_BTIJ  = 0x44 << 5,
> +	AARCH64_INSN_HINT_BTIJC = 0x4C << 5,

These constants are wrong (I checked the others, they're fine) - I'll
send out a fixed version as part of the next version of the BTI kernel
patches since they will depend on these.

Will Deacon April 28, 2020, 1:33 p.m. UTC | #2

On Tue, Apr 28, 2020 at 12:43:53PM +0100, Mark Brown wrote:
> On Tue, Mar 24, 2020 at 07:48:21PM +0000, Mark Brown wrote:
> 
> > +	AARCH64_INSN_HINT_BTI   = 0x40 << 5,
> > +	AARCH64_INSN_HINT_BTIC  = 0x42 << 5,
> > +	AARCH64_INSN_HINT_BTIJ  = 0x44 << 5,
> > +	AARCH64_INSN_HINT_BTIJC = 0x4C << 5,
> 
> These constants are wrong (I checked the others, they're fine) - I'll
> send out a fixed version as part of the next version of the BTI kernel
> patches since they will depend on these.

Ok, I'll ignore this series then.

Will

Patch

diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index bb313dde58a4..e88309ba06d9 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -39,13 +39,31 @@  enum aarch64_insn_encoding_class {
 					 * system instructions */
 };
 
-enum aarch64_insn_hint_op {
+enum aarch64_insn_hint_cr_op {
 	AARCH64_INSN_HINT_NOP	= 0x0 << 5,
 	AARCH64_INSN_HINT_YIELD	= 0x1 << 5,
 	AARCH64_INSN_HINT_WFE	= 0x2 << 5,
 	AARCH64_INSN_HINT_WFI	= 0x3 << 5,
 	AARCH64_INSN_HINT_SEV	= 0x4 << 5,
 	AARCH64_INSN_HINT_SEVL	= 0x5 << 5,
+
+	AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
+	AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
+	AARCH64_INSN_HINT_AUTIA_1716 = 0x0B << 5,
+	AARCH64_INSN_HINT_AUTIB_1716 = 0x0C << 5,
+	AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
+	AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
+	AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
+	AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
+	AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
+	AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,
+	AARCH64_INSN_HINT_AUTIBZ     = 0x1E << 5,
+	AARCH64_INSN_HINT_AUTIBSP    = 0x1F << 5,
+
+	AARCH64_INSN_HINT_BTI   = 0x40 << 5,
+	AARCH64_INSN_HINT_BTIC  = 0x42 << 5,
+	AARCH64_INSN_HINT_BTIJ  = 0x44 << 5,
+	AARCH64_INSN_HINT_BTIJC = 0x4C << 5,
 };
 
 enum aarch64_insn_imm_type {
@@ -370,7 +388,7 @@  u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
 				     enum aarch64_insn_branch_type type);
 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
 				     enum aarch64_insn_condition cond);
-u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
+u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op);
 u32 aarch64_insn_gen_nop(void);
 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
 				enum aarch64_insn_branch_type type);
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 535a3a7a053e..fd77cdd87c47 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -570,7 +570,7 @@  u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
 					     offset >> 2);
 }
 
-u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
+u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op)
 {
 	return aarch64_insn_get_hint_value() | op;
 }