| Message ID | 20200401132237.60880-12-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: dts: stm32: Repair AV96 board | expand |
On Wed, Apr 01, 2020 at 03:22:26PM +0200, Marek Vasut wrote: > The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it > into the DT. > > Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > Cc: Alexandre Torgue <alexandre.torgue@st.com> > Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> > Cc: Patrice Chotard <patrice.chotard@st.com> > Cc: Patrick Delaunay <patrick.delaunay@st.com> > Cc: linux-stm32@st-md-mailman.stormreply.com > To: linux-arm-kernel@lists.infradead.org > --- > V2: Use spi-flash in the DT node instead of explicit model name > V3: Reduce the SPI controller window to 2 MiB, which is the flash size > V4: Rebase on stm32-next > --- > arch/arm/boot/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts > index df68768e8a12..5831280f78ee 100644 > --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts > +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts > @@ -21,6 +21,7 @@ aliases { > mmc0 = &sdmmc1; > serial0 = &uart4; > serial1 = &uart7; > + spi0 = &qspi; > }; > > chosen { > @@ -312,6 +313,25 @@ &pwr_regulators { > vdd_3v3_usbfs-supply = <&vdd_usb>; > }; > > +&qspi { > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; > + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; > + reg = <0x58003000 0x1000>, <0x70000000 0x200000>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "okay"; > + > + flash0: spi-flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-rx-bus-width = <4>; > + spi-max-frequency = <108000000>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > +}; > + > &rng1 { > status = "okay"; > }; > -- > 2.25.1 >
diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index df68768e8a12..5831280f78ee 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -21,6 +21,7 @@ aliases { mmc0 = &sdmmc1; serial0 = &uart4; serial1 = &uart7; + spi0 = &qspi; }; chosen { @@ -312,6 +313,25 @@ &pwr_regulators { vdd_3v3_usbfs-supply = <&vdd_usb>; }; +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + &rng1 { status = "okay"; };
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it into the DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- V2: Use spi-flash in the DT node instead of explicit model name V3: Reduce the SPI controller window to 2 MiB, which is the flash size V4: Rebase on stm32-next --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)