| Message ID | 20200411074408.38090-5-jitao.shi@mediatek.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 424a3a706aac4ec70de4414f5bce62c09a3d76e1 |
| Headers | show |
| Series | Config mipi tx current and impedance | expand |
Hi, Jitao: Jitao Shi <jitao.shi@mediatek.com> 於 2020年4月11日 週六 下午3:45寫道： > > Read calibration data from nvmem, and config mipitx impedance with > calibration data to make sure their impedance are 100ohm. Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 40 +++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_mipi_tx.h | 3 ++ > drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 21 ++++++++++ > 3 files changed, 64 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c > index e301af64809e..8cee2591e728 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c > +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c > @@ -88,6 +88,44 @@ static const struct phy_ops mtk_mipi_tx_ops = { > .owner = THIS_MODULE, > }; > > +static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx) > +{ > + struct nvmem_cell *cell; > + size_t len; > + u32 *buf; > + > + cell = nvmem_cell_get(mipi_tx->dev, "calibration-data"); > + if (IS_ERR(cell)) { > + dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n"); > + return; > + } > + buf = (u32 *)nvmem_cell_read(cell, &len); > + nvmem_cell_put(cell); > + > + if (IS_ERR(buf)) { > + dev_info(mipi_tx->dev, "can't get data, ignore it\n"); > + return; > + } > + > + if (len < 3 * sizeof(u32)) { > + dev_info(mipi_tx->dev, "invalid calibration data\n"); > + kfree(buf); > + return; > + } > + > + mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | > + (buf[0] >> 11 & 0x1f); > + mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | > + (buf[0] >> 1 & 0x1f); > + mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | > + (buf[1] >> 22 & 0x1f); > + mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | > + (buf[1] >> 12 & 0x1f); > + mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | > + (buf[1] >> 2 & 0x1f); > + kfree(buf); > +} > + > static int mtk_mipi_tx_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > @@ -174,6 +212,8 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev) > > mipi_tx->dev = dev; > > + mtk_mipi_tx_get_calibration_datal(mipi_tx); > + > return of_clk_add_provider(dev->of_node, of_clk_src_simple_get, > mipi_tx->pll); > } > diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h > index eea44327fe9f..c76f07c3fdeb 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h > +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h > @@ -12,9 +12,11 @@ > #include <linux/delay.h> > #include <linux/io.h> > #include <linux/module.h> > +#include <linux/nvmem-consumer.h> > #include <linux/of_device.h> > #include <linux/platform_device.h> > #include <linux/phy/phy.h> > +#include <linux/slab.h> > > struct mtk_mipitx_data { > const u32 mppll_preserve; > @@ -28,6 +30,7 @@ struct mtk_mipi_tx { > void __iomem *regs; > u32 data_rate; > u32 mipitx_drive; > + u32 rt_code[5]; > const struct mtk_mipitx_data *driver_data; > struct clk_hw pll_hw; > struct clk *pll; > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > index e4cc967750cb..9f3e55aeebb2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > @@ -28,6 +28,7 @@ > #define MIPITX_PLL_CON4 0x003c > #define RG_DSI_PLL_IBIAS (3 << 10) > > +#define MIPITX_D2P_RTCODE 0x0100 > #define MIPITX_D2_SW_CTL_EN 0x0144 > #define MIPITX_D0_SW_CTL_EN 0x0244 > #define MIPITX_CK_CKMODE_EN 0x0328 > @@ -108,6 +109,24 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = { > .recalc_rate = mtk_mipi_tx_pll_recalc_rate, > }; > > +static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) > +{ > + int i, j; > + > + for (i = 0; i < 5; i++) { > + if ((mipi_tx->rt_code[i] & 0x1f) == 0) > + mipi_tx->rt_code[i] |= 0x10; > + > + if ((mipi_tx->rt_code[i] >> 5 & 0x1f) == 0) > + mipi_tx->rt_code[i] |= 0x10 << 5; > + > + for (j = 0; j < 10; j++) > + mtk_mipi_tx_update_bits(mipi_tx, > + MIPITX_D2P_RTCODE * (i + 1) + j * 4, > + 1, mipi_tx->rt_code[i] >> j & 1); > + } > +} > + > static void mtk_mipi_tx_power_on_signal(struct phy *phy) > { > struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); > @@ -130,6 +149,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) > RG_DSI_HSTX_LDO_REF_SEL, > (mipi_tx->mipitx_drive - 3000) / 200 << 6); > > + mtk_mipi_tx_config_calibration_data(mipi_tx); > + > mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); > } > > -- > 2.21.0 > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index e301af64809e..8cee2591e728 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -88,6 +88,44 @@ static const struct phy_ops mtk_mipi_tx_ops = { .owner = THIS_MODULE, }; +static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx) +{ + struct nvmem_cell *cell; + size_t len; + u32 *buf; + + cell = nvmem_cell_get(mipi_tx->dev, "calibration-data"); + if (IS_ERR(cell)) { + dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n"); + return; + } + buf = (u32 *)nvmem_cell_read(cell, &len); + nvmem_cell_put(cell); + + if (IS_ERR(buf)) { + dev_info(mipi_tx->dev, "can't get data, ignore it\n"); + return; + } + + if (len < 3 * sizeof(u32)) { + dev_info(mipi_tx->dev, "invalid calibration data\n"); + kfree(buf); + return; + } + + mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | + (buf[0] >> 11 & 0x1f); + mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | + (buf[0] >> 1 & 0x1f); + mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | + (buf[1] >> 22 & 0x1f); + mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | + (buf[1] >> 12 & 0x1f); + mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | + (buf[1] >> 2 & 0x1f); + kfree(buf); +} + static int mtk_mipi_tx_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -174,6 +212,8 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev) mipi_tx->dev = dev; + mtk_mipi_tx_get_calibration_datal(mipi_tx); + return of_clk_add_provider(dev->of_node, of_clk_src_simple_get, mipi_tx->pll); } diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h index eea44327fe9f..c76f07c3fdeb 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h @@ -12,9 +12,11 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/module.h> +#include <linux/nvmem-consumer.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/phy/phy.h> +#include <linux/slab.h> struct mtk_mipitx_data { const u32 mppll_preserve; @@ -28,6 +30,7 @@ struct mtk_mipi_tx { void __iomem *regs; u32 data_rate; u32 mipitx_drive; + u32 rt_code[5]; const struct mtk_mipitx_data *driver_data; struct clk_hw pll_hw; struct clk *pll; diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c index e4cc967750cb..9f3e55aeebb2 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c @@ -28,6 +28,7 @@ #define MIPITX_PLL_CON4 0x003c #define RG_DSI_PLL_IBIAS (3 << 10) +#define MIPITX_D2P_RTCODE 0x0100 #define MIPITX_D2_SW_CTL_EN 0x0144 #define MIPITX_D0_SW_CTL_EN 0x0244 #define MIPITX_CK_CKMODE_EN 0x0328 @@ -108,6 +109,24 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = { .recalc_rate = mtk_mipi_tx_pll_recalc_rate, }; +static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) +{ + int i, j; + + for (i = 0; i < 5; i++) { + if ((mipi_tx->rt_code[i] & 0x1f) == 0) + mipi_tx->rt_code[i] |= 0x10; + + if ((mipi_tx->rt_code[i] >> 5 & 0x1f) == 0) + mipi_tx->rt_code[i] |= 0x10 << 5; + + for (j = 0; j < 10; j++) + mtk_mipi_tx_update_bits(mipi_tx, + MIPITX_D2P_RTCODE * (i + 1) + j * 4, + 1, mipi_tx->rt_code[i] >> j & 1); + } +} + static void mtk_mipi_tx_power_on_signal(struct phy *phy) { struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); @@ -130,6 +149,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) RG_DSI_HSTX_LDO_REF_SEL, (mipi_tx->mipitx_drive - 3000) / 200 << 6); + mtk_mipi_tx_config_calibration_data(mipi_tx); + mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); }
Read calibration data from nvmem, and config mipitx impedance with calibration data to make sure their impedance are 100ohm. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 40 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_mipi_tx.h | 3 ++ drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 21 ++++++++++ 3 files changed, 64 insertions(+)