[V5,10/20] ARM: dts: stm32: Add QSPI NOR on AV96

Commit Message

Marek Vasut April 22, 2020, 10:46 a.m. UTC

The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it
into the DT.

Reviewed-by: Manivannan Sadhasivam <[e-mail]>
Signed-off-by: Marek Vasut <[e-mail]>
Cc: Alexandre Torgue <[e-mail]>
Cc: Manivannan Sadhasivam <[e-mail]>
Cc: Maxime Coquelin <[e-mail]>
Cc: Patrice Chotard <[e-mail]>
Cc: Patrick Delaunay <[e-mail]>
Cc: [e-mail]
To: [e-mail]
---
V2: Use spi-flash in the DT node instead of explicit model name
V3: Reduce the SPI controller window to 2 MiB, which is the flash size
V4: Rebase on stm32-next
V5: No change
---
 arch/arm/boot/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Patch

diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts
index 811cc4aff2a5..4043ab6d2ae6 100644
--- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts
@@ -21,6 +21,7 @@  aliases {
 		mmc0 = &sdmmc1;
 		serial0 = &uart4;
 		serial1 = &uart7;
+		spi0 = &qspi;
 	};
 
 	chosen {
@@ -314,6 +315,25 @@  &pwr_regulators {
 	vdd_3v3_usbfs-supply = <&vdd_usb>;
 };
 
+&qspi {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
+	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
+	reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash0: spi-flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <108000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
 &rng1 {
 	status = "okay";
 };