| Message ID | 20200504124442.208004-1-hsinyi@chromium.org (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 3b1f6c5e4dfaf767f6f2f120cd93b347b5a9f1aa |
| Headers | show |
| Series | arm64: dts: mt8173: fix vcodec-enc clock | expand |
On 04/05/2020 14:44, Hsin-Yi Wang wrote: > Fix the assigned-clock-parents to higher frequency clock to avoid h264 > encode timeout: > > [ 134.763465] mtk_vpu 10020000.vpu: vpu ipi 4 ack time out ! > [ 134.769008] [MTK_VCODEC][ERROR][18]: vpu_enc_send_msg() vpu_ipi_send msg_id c002 len 32 fail -5 > [ 134.777707] [MTK_VCODEC][ERROR][18]: vpu_enc_encode() AP_IPIMSG_ENC_ENCODE 0 fail > > venc_sel is the clock used by h264 encoder, and venclt_sel is the clock > used by vp8 encoder. Assign venc_sel to vcodecpll_ck and venclt_sel to > vcodecpll_370p5. > > vcodecpll 1482000000 > vcodecpll_ck 494000000 > venc_sel 494000000 > ... > vcodecpll_370p5 370500000 > venclt_sel 370500000 > > Fixes: fbbad0287cec ("arm64: dts: Using standard CCF interface to set vcodec clk") > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Applied to v5.7-fixes Thanks! > --- > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > index a212bf124e81..d0e9a2aada2e 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > @@ -1422,8 +1422,8 @@ vcodec_enc: vcodec@18002000 { > "venc_lt_sel"; > assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, > <&topckgen CLK_TOP_VENC_LT_SEL>; > - assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, > - <&topckgen CLK_TOP_UNIVPLL1_D2>; > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>, > + <&topckgen CLK_TOP_VCODECPLL_370P5>; > }; > > jpegdec: jpegdec@18004000 { >
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index a212bf124e81..d0e9a2aada2e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1422,8 +1422,8 @@ vcodec_enc: vcodec@18002000 { "venc_lt_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, <&topckgen CLK_TOP_VENC_LT_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, - <&topckgen CLK_TOP_UNIVPLL1_D2>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>, + <&topckgen CLK_TOP_VCODECPLL_370P5>; }; jpegdec: jpegdec@18004000 {
Fix the assigned-clock-parents to higher frequency clock to avoid h264 encode timeout: [ 134.763465] mtk_vpu 10020000.vpu: vpu ipi 4 ack time out ! [ 134.769008] [MTK_VCODEC][ERROR][18]: vpu_enc_send_msg() vpu_ipi_send msg_id c002 len 32 fail -5 [ 134.777707] [MTK_VCODEC][ERROR][18]: vpu_enc_encode() AP_IPIMSG_ENC_ENCODE 0 fail venc_sel is the clock used by h264 encoder, and venclt_sel is the clock used by vp8 encoder. Assign venc_sel to vcodecpll_ck and venclt_sel to vcodecpll_370p5. vcodecpll 1482000000 vcodecpll_ck 494000000 venc_sel 494000000 ... vcodecpll_370p5 370500000 venclt_sel 370500000 Fixes: fbbad0287cec ("arm64: dts: Using standard CCF interface to set vcodec clk") Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)