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[61.228.240.171]) by smtp.gmail.com with ESMTPSA id k27sm3768323pgb.30.2020.05.16.05.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 May 2020 05:50:10 -0700 (PDT) From: Lecopzer Chen To: linux-kernel@vger.kernel.org Subject: [PATCH 2/3] arm64: perf: Support NMI context for perf event ISR Date: Sat, 16 May 2020 20:48:56 +0800 Message-Id: <20200516124857.75004-3-lecopzer@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200516124857.75004-1-lecopzer@gmail.com> References: <20200516124857.75004-1-lecopzer@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200516_055011_702507_560D08F0 X-CRM114-Status: GOOD ( 12.49 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:543 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [lecopzer[at]gmail.com] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, lecopzer.chen@mediatek.com, Lecopzer Chen , alexander.shishkin@linux.intel.com, catalin.marinas@arm.com, jolsa@redhat.com, acme@kernel.org, peterz@infradead.org, mingo@redhat.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, namhyung@kernel.org, will@kernel.org, yj.chiang@mediatek.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Perf ISR doesn't support for NMI context, thus add some necessary condition-if to handle NMI context: - We should not hold pmu_lock since it may have already been acquired before NMI triggered. - irq_work should not run at NMI context. Signed-off-by: Lecopzer Chen --- arch/arm64/kernel/perf_event.c | 36 +++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 4d7879484cec..94b404509f02 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -313,6 +313,23 @@ static inline bool armv8pmu_event_is_chained(struct perf_event *event) (idx != ARMV8_IDX_CYCLE_COUNTER); } +/* + * NMI Perf interrupts may be triggered during kernel holding + * same lock. + * Avoid acquiring lock again in NMI context. + */ +#define armv8pmu_lock(lock, flags) \ + do { \ + if (!in_nmi()) \ + raw_spin_lock_irqsave(lock, flags); \ + } while (0) + +#define armv8pmu_unlock(lock, flags) \ + do { \ + if (!in_nmi()) \ + raw_spin_unlock_irqrestore(lock, flags);\ + } while (0) + /* * ARMv8 low level PMU access */ @@ -589,7 +606,7 @@ static void armv8pmu_enable_event(struct perf_event *event) * Enable counter and interrupt, and set the counter to count * the event that we're interested in. */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); + armv8pmu_lock(&events->pmu_lock, flags); /* * Disable counter @@ -611,7 +628,7 @@ static void armv8pmu_enable_event(struct perf_event *event) */ armv8pmu_enable_event_counter(event); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); + armv8pmu_unlock(&events->pmu_lock, flags); } static void armv8pmu_disable_event(struct perf_event *event) @@ -623,7 +640,7 @@ static void armv8pmu_disable_event(struct perf_event *event) /* * Disable counter and interrupt */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); + armv8pmu_lock(&events->pmu_lock, flags); /* * Disable counter @@ -635,7 +652,7 @@ static void armv8pmu_disable_event(struct perf_event *event) */ armv8pmu_disable_event_irq(event); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); + armv8pmu_unlock(&events->pmu_lock, flags); } static void armv8pmu_start(struct arm_pmu *cpu_pmu) @@ -643,10 +660,10 @@ static void armv8pmu_start(struct arm_pmu *cpu_pmu) unsigned long flags; struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); - raw_spin_lock_irqsave(&events->pmu_lock, flags); + armv8pmu_lock(&events->pmu_lock, flags); /* Enable all counters */ armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); + armv8pmu_unlock(&events->pmu_lock, flags); } static void armv8pmu_stop(struct arm_pmu *cpu_pmu) @@ -654,10 +671,10 @@ static void armv8pmu_stop(struct arm_pmu *cpu_pmu) unsigned long flags; struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); - raw_spin_lock_irqsave(&events->pmu_lock, flags); + armv8pmu_lock(&events->pmu_lock, flags); /* Disable all counters */ armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); + armv8pmu_unlock(&events->pmu_lock, flags); } static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) @@ -722,7 +739,8 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) * platforms that can have the PMU interrupts raised as an NMI, this * will not work. */ - irq_work_run(); + if (!armpmu_support_nmi()) + irq_work_run(); return IRQ_HANDLED; }