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Thu, 28 May 2020 09:40:10 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 197BE10003B; Thu, 28 May 2020 09:40:09 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node1.st.com [10.75.127.7]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E551A2B1885; Thu, 28 May 2020 09:40:08 +0200 (CEST) Received: from localhost (10.75.127.44) by SFHDAG3NODE1.st.com (10.75.127.7) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 28 May 2020 09:40:08 +0200 From: Erwan Le Ray To: Maxime Coquelin , Alexandre Torgue , Rob Herring , Mark Rutland Subject: [PATCH 1/2] ARM: dts: stm32: fix uart nodes ordering in stm32mp15-pinctrl Date: Thu, 28 May 2020 09:40:02 +0200 Message-ID: <20200528074003.24875-2-erwan.leray@st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200528074003.24875-1-erwan.leray@st.com> References: <20200528074003.24875-1-erwan.leray@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG7NODE1.st.com (10.75.127.19) To SFHDAG3NODE1.st.com (10.75.127.7) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-05-28_02:2020-05-28, 2020-05-27 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200528_004015_364981_5FD98BD8 X-CRM114-Status: GOOD ( 11.67 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [62.209.51.94 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Fabrice Gasnier , linux-stm32@st-md-mailman.stormreply.com, Erwan Le Ray Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Fix usart and uart nodes ordering. Several usart nodes didn't respect expecting ordering. Fixes: 077e0638fc83 ("ARM: dts: stm32: Add alternate pinmux for USART2 pins on stm32mp15") Signed-off-by: Erwan Le Ray diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 7cf535dc05f5..5ff1323236e1 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1574,67 +1574,6 @@ }; }; - usart2_pins_a: usart2-0 { - pins1 { - pinmux = , /* USART2_TX */ - ; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_sleep_pins_a: usart2-sleep-0 { - pins { - pinmux = , /* USART2_TX */ - , /* USART2_RTS */ - , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - }; - }; - - usart2_pins_b: usart2-1 { - pins1 { - pinmux = , /* USART2_TX */ - ; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_sleep_pins_b: usart2-sleep-1 { - pins { - pinmux = , /* USART2_TX */ - , /* USART2_RTS */ - , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - }; - }; - - usart3_pins_a: usart3-0 { - pins1 { - pinmux = ; /* USART3_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART3_RX */ - bias-disable; - }; - }; - uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ @@ -1732,6 +1671,67 @@ }; }; + usart2_pins_a: usart2-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + + usart2_pins_b: usart2-1 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + + usart3_pins_a: usart3-0 { + pins1 { + pinmux = ; /* USART3_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = ; /* OTG_ID */