diff mbox series

[2/2] clk: bcm63xx-gate: add BCM6318 support

Message ID 20200609113049.4035426-3-noltari@gmail.com
State New, archived
Headers show
Series clk: bcm63xx-gate: add BCM6318 support | expand

Commit Message

Álvaro Fernández Rojas June 9, 2020, 11:30 a.m. UTC
Add support for the gated clock controllers found on the BCM6318.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 drivers/clk/bcm/clk-bcm63xx-gate.c | 44 ++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

Comments

Florian Fainelli June 10, 2020, 2:27 a.m. UTC | #1
On 6/9/2020 4:30 AM, Álvaro Fernández Rojas wrote:
> +static const struct clk_bcm63xx_table_entry bcm6318_clocks[] = {
> +	{ .name = "adsl_asb", .bit = 0, },
> +	{ .name = "usb_asb", .bit = 1, },
> +	{ .name = "mips_asb", .bit = 2, },
> +	{ .name = "pcie_asb", .bit = 3, },
> +	{ .name = "phymips_asb", .bit = 4, },
> +	{ .name = "robosw_asb", .bit = 5, },
> +	{ .name = "sar_asb", .bit = 6, },
> +	{ .name = "sdr_asb", .bit = 7, },
> +	{ .name = "swreg_asb", .bit = 8, },
> +	{ .name = "periph_asb", .bit = 9, },
> +	{ .name = "cpubus160", .bit = 10, },
> +	{ .name = "adsl", .bit = 11, },
> +	{ .name = "sar124", .bit = 12, },

Nit: this should be sar125

> +	{ .name = "mips", .bit = 13, .flags = CLK_IS_CRITICAL, },
> +	{ .name = "pcie", .bit = 14, },
> +	{ .name = "robosw250", .bit = 16, },
> +	{ .name = "robosw025", .bit = 17, },
> +	{ .name = "sdr", .bit = 19, .flags = CLK_IS_CRITICAL, },
> +	{ .name = "usb", .bit = 20, },

This should probably be "usbd" to indicate this is the USB device clock
(not host)

With that fixed:

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Álvaro Fernández Rojas June 10, 2020, 6:12 a.m. UTC | #2
Hi Florian,

> El 10 jun 2020, a las 4:27, Florian Fainelli <f.fainelli@gmail.com> escribió:
> 
> 
> 
> On 6/9/2020 4:30 AM, Álvaro Fernández Rojas wrote:
>> +static const struct clk_bcm63xx_table_entry bcm6318_clocks[] = {
>> +	{ .name = "adsl_asb", .bit = 0, },
>> +	{ .name = "usb_asb", .bit = 1, },
>> +	{ .name = "mips_asb", .bit = 2, },
>> +	{ .name = "pcie_asb", .bit = 3, },
>> +	{ .name = "phymips_asb", .bit = 4, },
>> +	{ .name = "robosw_asb", .bit = 5, },
>> +	{ .name = "sar_asb", .bit = 6, },
>> +	{ .name = "sdr_asb", .bit = 7, },
>> +	{ .name = "swreg_asb", .bit = 8, },
>> +	{ .name = "periph_asb", .bit = 9, },
>> +	{ .name = "cpubus160", .bit = 10, },
>> +	{ .name = "adsl", .bit = 11, },
>> +	{ .name = "sar124", .bit = 12, },
> 
> Nit: this should be sar125

Nice catch, I will fix this in v2.

> 
>> +	{ .name = "mips", .bit = 13, .flags = CLK_IS_CRITICAL, },
>> +	{ .name = "pcie", .bit = 14, },
>> +	{ .name = "robosw250", .bit = 16, },
>> +	{ .name = "robosw025", .bit = 17, },
>> +	{ .name = "sdr", .bit = 19, .flags = CLK_IS_CRITICAL, },
>> +	{ .name = "usb", .bit = 20, },
> 
> This should probably be "usbd" to indicate this is the USB device clock
> (not host)

Ok, I will change it. I got confused by the fact that both (usbd and usbh) were present on 6318_map_part.h:
#define USBD_CLK_EN         (1 << 20)
#define USBH_CLK_EN         (1 << 20)

> 
> With that fixed:
> 
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
> -- 
> Florian
Philippe Mathieu-Daudé June 10, 2020, 8:29 a.m. UTC | #3
Hi,

On Wed, Jun 10, 2020 at 8:13 AM Álvaro Fernández Rojas
<noltari@gmail.com> wrote:
>
> Hi Florian,
>
> > El 10 jun 2020, a las 4:27, Florian Fainelli <f.fainelli@gmail.com> escribió:
> >
> >
> >
> > On 6/9/2020 4:30 AM, Álvaro Fernández Rojas wrote:
> >> +static const struct clk_bcm63xx_table_entry bcm6318_clocks[] = {
> >> +    { .name = "adsl_asb", .bit = 0, },
> >> +    { .name = "usb_asb", .bit = 1, },
> >> +    { .name = "mips_asb", .bit = 2, },
> >> +    { .name = "pcie_asb", .bit = 3, },
> >> +    { .name = "phymips_asb", .bit = 4, },
> >> +    { .name = "robosw_asb", .bit = 5, },
> >> +    { .name = "sar_asb", .bit = 6, },
> >> +    { .name = "sdr_asb", .bit = 7, },
> >> +    { .name = "swreg_asb", .bit = 8, },
> >> +    { .name = "periph_asb", .bit = 9, },
> >> +    { .name = "cpubus160", .bit = 10, },
> >> +    { .name = "adsl", .bit = 11, },
> >> +    { .name = "sar124", .bit = 12, },
> >
> > Nit: this should be sar125
>
> Nice catch, I will fix this in v2.
>
> >
> >> +    { .name = "mips", .bit = 13, .flags = CLK_IS_CRITICAL, },
> >> +    { .name = "pcie", .bit = 14, },
> >> +    { .name = "robosw250", .bit = 16, },
> >> +    { .name = "robosw025", .bit = 17, },
> >> +    { .name = "sdr", .bit = 19, .flags = CLK_IS_CRITICAL, },
> >> +    { .name = "usb", .bit = 20, },
> >
> > This should probably be "usbd" to indicate this is the USB device clock
> > (not host)
>
> Ok, I will change it. I got confused by the fact that both (usbd and usbh) were present on 6318_map_part.h:
> #define USBD_CLK_EN         (1 << 20)
> #define USBH_CLK_EN         (1 << 20)

Is there a datasheet to verify that?

>
> >
> > With that fixed:
> >
> > Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
> > --
> > Florian
>
Florian Fainelli June 10, 2020, 3:14 p.m. UTC | #4
On 6/10/2020 1:29 AM, Philippe Mathieu-Daudé wrote:
> Hi,
> 
> On Wed, Jun 10, 2020 at 8:13 AM Álvaro Fernández Rojas
> <noltari@gmail.com> wrote:
>>
>> Hi Florian,
>>
>>> El 10 jun 2020, a las 4:27, Florian Fainelli <f.fainelli@gmail.com> escribió:
>>>
>>>
>>>
>>> On 6/9/2020 4:30 AM, Álvaro Fernández Rojas wrote:
>>>> +static const struct clk_bcm63xx_table_entry bcm6318_clocks[] = {
>>>> +    { .name = "adsl_asb", .bit = 0, },
>>>> +    { .name = "usb_asb", .bit = 1, },
>>>> +    { .name = "mips_asb", .bit = 2, },
>>>> +    { .name = "pcie_asb", .bit = 3, },
>>>> +    { .name = "phymips_asb", .bit = 4, },
>>>> +    { .name = "robosw_asb", .bit = 5, },
>>>> +    { .name = "sar_asb", .bit = 6, },
>>>> +    { .name = "sdr_asb", .bit = 7, },
>>>> +    { .name = "swreg_asb", .bit = 8, },
>>>> +    { .name = "periph_asb", .bit = 9, },
>>>> +    { .name = "cpubus160", .bit = 10, },
>>>> +    { .name = "adsl", .bit = 11, },
>>>> +    { .name = "sar124", .bit = 12, },
>>>
>>> Nit: this should be sar125
>>
>> Nice catch, I will fix this in v2.
>>
>>>
>>>> +    { .name = "mips", .bit = 13, .flags = CLK_IS_CRITICAL, },
>>>> +    { .name = "pcie", .bit = 14, },
>>>> +    { .name = "robosw250", .bit = 16, },
>>>> +    { .name = "robosw025", .bit = 17, },
>>>> +    { .name = "sdr", .bit = 19, .flags = CLK_IS_CRITICAL, },
>>>> +    { .name = "usb", .bit = 20, },
>>>
>>> This should probably be "usbd" to indicate this is the USB device clock
>>> (not host)
>>
>> Ok, I will change it. I got confused by the fact that both (usbd and usbh) were present on 6318_map_part.h:
>> #define USBD_CLK_EN         (1 << 20)
>> #define USBH_CLK_EN         (1 << 20)
> 
> Is there a datasheet to verify that?

Not a public one, but I can confirm this is correct given the internal
datasheet.
Philippe Mathieu-Daudé June 13, 2020, 5:53 p.m. UTC | #5
On Wed, Jun 10, 2020 at 5:32 PM Florian Fainelli <f.fainelli@gmail.com> wrote:
> On 6/10/2020 1:29 AM, Philippe Mathieu-Daudé wrote:
> > Hi,
> >
> > On Wed, Jun 10, 2020 at 8:13 AM Álvaro Fernández Rojas
> > <noltari@gmail.com> wrote:
> >>
> >> Hi Florian,
> >>
> >>> El 10 jun 2020, a las 4:27, Florian Fainelli <f.fainelli@gmail.com> escribió:
> >>>
> >>>
> >>>
> >>> On 6/9/2020 4:30 AM, Álvaro Fernández Rojas wrote:
> >>>> +static const struct clk_bcm63xx_table_entry bcm6318_clocks[] = {
> >>>> +    { .name = "adsl_asb", .bit = 0, },
> >>>> +    { .name = "usb_asb", .bit = 1, },
> >>>> +    { .name = "mips_asb", .bit = 2, },
> >>>> +    { .name = "pcie_asb", .bit = 3, },
> >>>> +    { .name = "phymips_asb", .bit = 4, },
> >>>> +    { .name = "robosw_asb", .bit = 5, },
> >>>> +    { .name = "sar_asb", .bit = 6, },
> >>>> +    { .name = "sdr_asb", .bit = 7, },
> >>>> +    { .name = "swreg_asb", .bit = 8, },
> >>>> +    { .name = "periph_asb", .bit = 9, },
> >>>> +    { .name = "cpubus160", .bit = 10, },
> >>>> +    { .name = "adsl", .bit = 11, },
> >>>> +    { .name = "sar124", .bit = 12, },
> >>>
> >>> Nit: this should be sar125
> >>
> >> Nice catch, I will fix this in v2.
> >>
> >>>
> >>>> +    { .name = "mips", .bit = 13, .flags = CLK_IS_CRITICAL, },
> >>>> +    { .name = "pcie", .bit = 14, },
> >>>> +    { .name = "robosw250", .bit = 16, },
> >>>> +    { .name = "robosw025", .bit = 17, },
> >>>> +    { .name = "sdr", .bit = 19, .flags = CLK_IS_CRITICAL, },
> >>>> +    { .name = "usb", .bit = 20, },
> >>>
> >>> This should probably be "usbd" to indicate this is the USB device clock
> >>> (not host)
> >>
> >> Ok, I will change it. I got confused by the fact that both (usbd and usbh) were present on 6318_map_part.h:
> >> #define USBD_CLK_EN         (1 << 20)
> >> #define USBH_CLK_EN         (1 << 20)
> >
> > Is there a datasheet to verify that?
>
> Not a public one, but I can confirm this is correct given the internal
> datasheet.

OK thank you Florian.

> --
> Florian
diff mbox series

Patch

diff --git a/drivers/clk/bcm/clk-bcm63xx-gate.c b/drivers/clk/bcm/clk-bcm63xx-gate.c
index 98e884957db8..12394c091d13 100644
--- a/drivers/clk/bcm/clk-bcm63xx-gate.c
+++ b/drivers/clk/bcm/clk-bcm63xx-gate.c
@@ -40,6 +40,48 @@  static const struct clk_bcm63xx_table_entry bcm3368_clocks[] = {
 	{ },
 };
 
+static const struct clk_bcm63xx_table_entry bcm6318_clocks[] = {
+	{ .name = "adsl_asb", .bit = 0, },
+	{ .name = "usb_asb", .bit = 1, },
+	{ .name = "mips_asb", .bit = 2, },
+	{ .name = "pcie_asb", .bit = 3, },
+	{ .name = "phymips_asb", .bit = 4, },
+	{ .name = "robosw_asb", .bit = 5, },
+	{ .name = "sar_asb", .bit = 6, },
+	{ .name = "sdr_asb", .bit = 7, },
+	{ .name = "swreg_asb", .bit = 8, },
+	{ .name = "periph_asb", .bit = 9, },
+	{ .name = "cpubus160", .bit = 10, },
+	{ .name = "adsl", .bit = 11, },
+	{ .name = "sar124", .bit = 12, },
+	{ .name = "mips", .bit = 13, .flags = CLK_IS_CRITICAL, },
+	{ .name = "pcie", .bit = 14, },
+	{ .name = "robosw250", .bit = 16, },
+	{ .name = "robosw025", .bit = 17, },
+	{ .name = "sdr", .bit = 19, .flags = CLK_IS_CRITICAL, },
+	{ .name = "usb", .bit = 20, },
+	{ .name = "hsspi", .bit = 25, },
+	{ .name = "pcie25", .bit = 27, },
+	{ .name = "phymips", .bit = 28, },
+	{ .name = "afe", .bit = 29, },
+	{ .name = "qproc", .bit = 30, },
+	{ },
+};
+
+static const struct clk_bcm63xx_table_entry bcm6318_ubus_clocks[] = {
+	{ .name = "adsl-ubus", .bit = 0, },
+	{ .name = "arb-ubus", .bit = 1, .flags = CLK_IS_CRITICAL, },
+	{ .name = "mips-ubus", .bit = 2, .flags = CLK_IS_CRITICAL, },
+	{ .name = "pcie-ubus", .bit = 3, },
+	{ .name = "periph-ubus", .bit = 4, .flags = CLK_IS_CRITICAL, },
+	{ .name = "phymips-ubus", .bit = 5, },
+	{ .name = "robosw-ubus", .bit = 6, },
+	{ .name = "sar-ubus", .bit = 7, },
+	{ .name = "sdr-ubus", .bit = 8, },
+	{ .name = "usb-ubus", .bit = 9, },
+	{ },
+};
+
 static const struct clk_bcm63xx_table_entry bcm6328_clocks[] = {
 	{ .name = "phy_mips", .bit = 0, },
 	{ .name = "adsl_qproc", .bit = 1, },
@@ -217,6 +259,8 @@  static int clk_bcm63xx_remove(struct platform_device *pdev)
 
 static const struct of_device_id clk_bcm63xx_dt_ids[] = {
 	{ .compatible = "brcm,bcm3368-clocks", .data = &bcm3368_clocks, },
+	{ .compatible = "brcm,bcm6318-clocks", .data = &bcm6318_clocks, },
+	{ .compatible = "brcm,bcm6318-ubus-clocks", .data = &bcm6318_ubus_clocks, },
 	{ .compatible = "brcm,bcm6328-clocks", .data = &bcm6328_clocks, },
 	{ .compatible = "brcm,bcm6358-clocks", .data = &bcm6358_clocks, },
 	{ .compatible = "brcm,bcm6362-clocks", .data = &bcm6362_clocks, },