diff mbox series

net: mvneta: Fix Serdes configuration for 2.5Gbps modes

Message ID 20200609131152.22836-1-s.hauer@pengutronix.de (mailing list archive)
State New, archived
Headers show
Series net: mvneta: Fix Serdes configuration for 2.5Gbps modes | expand

Commit Message

Sascha Hauer June 9, 2020, 1:11 p.m. UTC
The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
called DRSGMII. Depending on the Port MAC Control Register0 PortType
setting this seems to be either an overclocked SGMII mode or 2500BaseX.

This patch adds the necessary Serdes Configuration setting for the
2.5Gbps modes. There is no phy interface mode define for overclocked
SGMII, so only 2500BaseX is handled for now.

As phy_interface_mode_is_8023z() returns true for both
PHY_INTERFACE_MODE_1000BASEX and PHY_INTERFACE_MODE_2500BASEX we
explicitly test for 1000BaseX instead of using
phy_interface_mode_is_8023z() to differentiate the different
possibilities.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/net/ethernet/marvell/mvneta.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Andrew Lunn June 9, 2020, 1:28 p.m. UTC | #1
On Tue, Jun 09, 2020 at 03:11:52PM +0200, Sascha Hauer wrote:
> The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> called DRSGMII. Depending on the Port MAC Control Register0 PortType
> setting this seems to be either an overclocked SGMII mode or 2500BaseX.
> 
> This patch adds the necessary Serdes Configuration setting for the
> 2.5Gbps modes. There is no phy interface mode define for overclocked
> SGMII, so only 2500BaseX is handled for now.
> 
> As phy_interface_mode_is_8023z() returns true for both
> PHY_INTERFACE_MODE_1000BASEX and PHY_INTERFACE_MODE_2500BASEX we
> explicitly test for 1000BaseX instead of using
> phy_interface_mode_is_8023z() to differentiate the different
> possibilities.

Hi Sascha

This seems like it should have a Fixes: tag, and be submitted to the
net tree. Please see the Networking FAQ.

Otherwise it looks O.K.

    Andrew
Sascha Hauer June 10, 2020, 6:26 a.m. UTC | #2
Hi Andrew,

+Cc Maxime Chevallier

On Tue, Jun 09, 2020 at 03:28:48PM +0200, Andrew Lunn wrote:
> On Tue, Jun 09, 2020 at 03:11:52PM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> > called DRSGMII. Depending on the Port MAC Control Register0 PortType
> > setting this seems to be either an overclocked SGMII mode or 2500BaseX.
> > 
> > This patch adds the necessary Serdes Configuration setting for the
> > 2.5Gbps modes. There is no phy interface mode define for overclocked
> > SGMII, so only 2500BaseX is handled for now.
> > 
> > As phy_interface_mode_is_8023z() returns true for both
> > PHY_INTERFACE_MODE_1000BASEX and PHY_INTERFACE_MODE_2500BASEX we
> > explicitly test for 1000BaseX instead of using
> > phy_interface_mode_is_8023z() to differentiate the different
> > possibilities.
> 
> Hi Sascha
> 
> This seems like it should have a Fixes: tag, and be submitted to the
> net tree. Please see the Networking FAQ.

This might be a candidate for a Fixes: tag:

| commit da58a931f248f423f917c3a0b3c94303aa30a738
| Author: Maxime Chevallier <maxime.chevallier@bootlin.com>
| Date:   Tue Sep 25 15:59:39 2018 +0200
| 
|     net: mvneta: Add support for 2500Mbps SGMII

What do you mean by "submitted to the net tree"? I usually send network
driver related patches to netdev@vger.kernel.org and from there David
applies them. Is there anything more to it I haven't respected?

Sascha
Florian Fainelli June 10, 2020, 3:24 p.m. UTC | #3
On 6/9/2020 11:26 PM, Sascha Hauer wrote:
> Hi Andrew,
> 
> +Cc Maxime Chevallier
> 
> On Tue, Jun 09, 2020 at 03:28:48PM +0200, Andrew Lunn wrote:
>> On Tue, Jun 09, 2020 at 03:11:52PM +0200, Sascha Hauer wrote:
>>> The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
>>> called DRSGMII. Depending on the Port MAC Control Register0 PortType
>>> setting this seems to be either an overclocked SGMII mode or 2500BaseX.
>>>
>>> This patch adds the necessary Serdes Configuration setting for the
>>> 2.5Gbps modes. There is no phy interface mode define for overclocked
>>> SGMII, so only 2500BaseX is handled for now.
>>>
>>> As phy_interface_mode_is_8023z() returns true for both
>>> PHY_INTERFACE_MODE_1000BASEX and PHY_INTERFACE_MODE_2500BASEX we
>>> explicitly test for 1000BaseX instead of using
>>> phy_interface_mode_is_8023z() to differentiate the different
>>> possibilities.
>>
>> Hi Sascha
>>
>> This seems like it should have a Fixes: tag, and be submitted to the
>> net tree. Please see the Networking FAQ.
> 
> This might be a candidate for a Fixes: tag:
> 
> | commit da58a931f248f423f917c3a0b3c94303aa30a738
> | Author: Maxime Chevallier <maxime.chevallier@bootlin.com>
> | Date:   Tue Sep 25 15:59:39 2018 +0200
> | 
> |     net: mvneta: Add support for 2500Mbps SGMII
> 
> What do you mean by "submitted to the net tree"? I usually send network
> driver related patches to netdev@vger.kernel.org and from there David
> applies them. Is there anything more to it I haven't respected?

Here are relevant bits from the netdev-FAQ:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/networking/netdev-FAQ.rst#n28

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/networking/netdev-FAQ.rst#n78

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/networking/netdev-FAQ.rst#n210
diff mbox series

Patch

diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 51889770958d8..3b13048931412 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -109,6 +109,7 @@ 
 #define MVNETA_SERDES_CFG			 0x24A0
 #define      MVNETA_SGMII_SERDES_PROTO		 0x0cc7
 #define      MVNETA_QSGMII_SERDES_PROTO		 0x0667
+#define      MVNETA_DRSGMII_SERDES_PROTO	 0x1107
 #define MVNETA_TYPE_PRIO                         0x24bc
 #define      MVNETA_FORCE_UNI                    BIT(21)
 #define MVNETA_TXQ_CMD_1                         0x24e4
@@ -4966,8 +4967,10 @@  static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
 	if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
 		mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
 	else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
-		 phy_interface_mode_is_8023z(phy_mode))
+		 phy_mode == PHY_INTERFACE_MODE_1000BASEX)
 		mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
+	else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX)
+		mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_DRSGMII_SERDES_PROTO);
 	else if (!phy_interface_mode_is_rgmii(phy_mode))
 		return -EINVAL;