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[114.171.61.116]) by smtp.googlemail.com with ESMTPSA id nl8sm5191620pjb.13.2020.06.10.02.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 02:08:28 -0700 (PDT) From: Daniel Palmer To: Subject: [PATCH v2 2/5] ARM: mstar: Add machine for MStar/Sigmastar infinity/mercury family ARMv7 SoCs Date: Wed, 10 Jun 2020 18:04:00 +0900 Message-Id: <20200610090421.3428945-3-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20191014061617.10296-2-daniel@0x0f.com> References: <20191014061617.10296-2-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200610_020830_433228_E648FDEC X-CRM114-Status: GOOD ( 20.58 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:644 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linus Walleij , Masahiro Yamada , Daniel Palmer , Benjamin Gaignard , Sam Ravnborg , Ard Biesheuvel , Stephan Gerhold , Jonathan Corbet , Mauro Carvalho Chehab , Heiko Stuebner , daniel@0x0f.com, Russell King , Bartosz Golaszewski , linux-arm-kernel@lists.infradead.org, Nathan Huckleberry , devicetree@vger.kernel.org, Arnd Bergmann , allen , tim.bird@sony.com, Maxime Ripard , Lubomir Rintel , Rob Herring , Gregory Fong , Doug Anderson , Nathan Chancellor , k@japko.eu, Christian Lamparter , Greg Kroah-Hartman , Nick Desaulniers , linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Mark Brown , Marc Zyngier , Andrew Morton , "David S. Miller" , Mike Rapoport Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Initial support for the MStar/Sigmastar infinity/mercury series of ARMv7 based IP camera and dashcam SoCs. These chips are interesting in that they contain a Cortex A7, peripherals and system memory in a single tiny QFN package that can be hand soldered allowing almost anyone to embed Linux in their projects. Signed-off-by: Daniel Palmer --- MAINTAINERS | 1 + arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/mach-mstar/Kconfig | 26 +++++++++++++ arch/arm/mach-mstar/Makefile | 1 + arch/arm/mach-mstar/mstarv7.c | 72 +++++++++++++++++++++++++++++++++++ 6 files changed, 103 insertions(+) create mode 100644 arch/arm/mach-mstar/Kconfig create mode 100644 arch/arm/mach-mstar/Makefile create mode 100644 arch/arm/mach-mstar/mstarv7.c diff --git a/MAINTAINERS b/MAINTAINERS index 1ca77f97b8ee..754521938303 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2114,6 +2114,7 @@ ARM/MStar/Sigmastar ARMv7 SoC support M: Daniel Palmer L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: arch/arm/mach-mstar/ F: Documentation/devicetree/bindings/arm/mstar.yaml ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fb6c85c5d344..e466694f8486 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -669,6 +669,8 @@ source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-moxart/Kconfig" +source "arch/arm/mach-mstar/Kconfig" + source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/mach-mvebu/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 59fde2d598d8..e7f4ca060c0f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -197,6 +197,7 @@ machine-$(CONFIG_ARCH_MXC) += imx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut machine-$(CONFIG_ARCH_MXS) += mxs +machine-$(CONFIG_ARCH_MSTARV7) += mstar machine-$(CONFIG_ARCH_NOMADIK) += nomadik machine-$(CONFIG_ARCH_NPCM) += npcm machine-$(CONFIG_ARCH_NSPIRE) += nspire diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig new file mode 100644 index 000000000000..6235d0a7860a --- /dev/null +++ b/arch/arm/mach-mstar/Kconfig @@ -0,0 +1,26 @@ +menuconfig ARCH_MSTARV7 + bool "MStar/Sigmastar ARMv7 SoC Support" + depends on ARCH_MULTI_V7 + select ARM_GIC + select ARM_HEAVY_MB + help + Support for newer MStar/Sigmastar SoC families that are + based on ARMv7 cores like the Cortex A7 and share the same + basic hardware like the infinity and mercury series. + +if ARCH_MSTARV7 + +config MACH_INFINITY + bool "MStar/Sigmastar infinity SoC support" + default ARCH_MSTARV7 + help + Support for MStar/Sigmastar infinity IP camera SoCs. + +config MACH_MERCURY + bool "MStar/Sigmastar mercury SoC support" + default ARCH_MSTARV7 + help + Support for MStar/Sigmastar mercury dash camera SoCs. + Note that older Mercury2 SoCs are ARM9 based and not supported. + +endif diff --git a/arch/arm/mach-mstar/Makefile b/arch/arm/mach-mstar/Makefile new file mode 100644 index 000000000000..93b0391ede7e --- /dev/null +++ b/arch/arm/mach-mstar/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_MSTARV7) += mstarv7.o diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c new file mode 100644 index 000000000000..ee96ce46cbbc --- /dev/null +++ b/arch/arm/mach-mstar/mstarv7.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree support for MStar/Sigmastar ARMv7 SoCs + * + * Copyright (c) 2019 thingy.jp + * Author: Daniel Palmer + */ + +#include +#include +#include +#include +#include + +/* + * In the u-boot code the area these registers are in is + * called "L3 bridge" and there are register descriptions + * for something in the same area called "AXI". + * + * It's not exactly known what this is but the vendor code + * for both u-boot and linux share calls to "flush the miu pipe". + * This seems to be to force pending CPU writes to memory so that + * the state is right before DMA capable devices try to read + * descriptors and data the CPU has prepared. Without doing this + * ethernet doesn't work reliably for example. + */ + +#define MSTARV7_L3BRIDGE_FLUSH 0x1f204414 +#define MSTARV7_L3BRIDGE_STATUS 0x1f204440 +#define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0) +#define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12) + +static u32 __iomem *miu_status; +static u32 __iomem *miu_flush; + +static const char * const mstarv7_board_dt_compat[] __initconst = { + "mstar,infinity", + "mstar,infinity3", + "mstar,mercury5", + NULL, +}; + +/* + * This may need locking to deal with situations where an interrupt + * happens while we are in here and mb() gets called by the interrupt handler. + */ +static void mstarv7_mb(void) +{ + /* toggle the flush miu pipe fire bit */ + writel_relaxed(0, miu_flush); + writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, miu_flush); + while (!(readl_relaxed(miu_status) & MSTARV7_L3BRIDGE_STATUS_DONE)) { + /* wait for flush to complete */ + } +} + +static void __init mstarv7_barriers_init(void) +{ + miu_flush = ioremap(MSTARV7_L3BRIDGE_FLUSH, sizeof(*miu_flush)); + miu_status = ioremap(MSTARV7_L3BRIDGE_STATUS, sizeof(*miu_status)); + soc_mb = mstarv7_mb; +} + +static void __init mstarv7_init(void) +{ + mstarv7_barriers_init(); +} + +DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar ARMv7 (Device Tree)") + .dt_compat = mstarv7_board_dt_compat, + .init_machine = mstarv7_init, +MACHINE_END