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Thu, 18 Jun 2020 02:52:00 -0700 (PDT) Date: Thu, 18 Jun 2020 18:51:55 +0900 From: Hyeonki Hong To: Rob Herring , Kevin Hilman Subject: [PATCH] arm64: dts: odroid: add spicc0 controller node Message-ID: <20200618095150.GA9713@home-desktop> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200618_025202_258754_AE256B00 X-CRM114-Status: GOOD ( 12.23 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:444 listed in] [list.dnswl.org] 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [hhk7734[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [hhk7734[at]gmail.com] -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add enabled spicc0 controller node with annotations describing the physical SPI0 pin number based on the 40 pin header on the Odroid board. Signed-off-by: Hyeonki Hong Reported-by: kernel test robot --- .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 26 +++++++++++++++++-- .../boot/dts/amlogic/meson-sm1-odroid-c4.dts | 24 ++++++++++++++++- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts index 169ea283d4ee..ec6d345caaae 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts @@ -16,8 +16,9 @@ model = "Hardkernel ODROID-N2"; aliases { - serial0 = &uart_AO; ethernet0 = ðmac; + serial0 = &uart_AO; + spi0 = &spicc0 }; chosen { @@ -328,7 +329,7 @@ &ext_mdio { external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ + /* Realtek RTL8211F (0x001cc916) */ reg = <0>; max-speed = <1000>; @@ -451,6 +452,27 @@ vqmmc-supply = <&flash_1v8>; }; +&spicc0 { + status = "okay"; + + /* + * 40 Pin Header : MOSI(GPIOX.8->19 Pin), + * MISO(GPIOX.9->21 Pin), + * SPI0_CLK(GPIOX.11->23 Pin) + * SPI_CE0(GPIOX.10->24 Pin), + */ + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_x_pins>, <&spicc0_ss0_x_pins>; + + spidev@0 { + compatible = "spidev"; + status = "okay"; + /* spi default max clock 100Mhz */ + spi-max-frequency = <100000000>; + reg = <0>; + }; +}; + /* * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins * and eMMC Data 4 to 7 pins. diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts index 00d90b30f8b4..f809b2ba6b15 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts @@ -14,8 +14,9 @@ model = "Hardkernel ODROID-C4"; aliases { - serial0 = &uart_AO; ethernet0 = ðmac; + serial0 = &uart_AO; + spi0 = &spicc0; }; chosen { @@ -381,6 +382,27 @@ vqmmc-supply = <&flash_1v8>; }; +&spicc0 { + status = "okay"; + + /* + * 40 Pin Header : MOSI(GPIOX.8->19 Pin), + * MISO(GPIOX.9->21 Pin), + * SPI0_CLK(GPIOX.11->23 Pin) + * SPI_CE0(GPIOX.10->24 Pin), + */ + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_x_pins>, <&spicc0_ss0_x_pins>; + + spidev@0 { + compatible = "spidev"; + status = "okay"; + /* spi default max clock 100Mhz */ + spi-max-frequency = <100000000>; + reg = <0>; + }; +}; + &uart_AO { status = "okay"; pinctrl-0 = <&uart_ao_a_pins>;