From patchwork Thu Jun 25 13:37:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 11625391 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0311914B7 for ; Thu, 25 Jun 2020 13:45:52 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D00DA20781 for ; Thu, 25 Jun 2020 13:45:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="kujlh78G" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D00DA20781 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=AL/xmIp6uOQB1W2ItD5cyMP9hy8rRGexp48vYR499ys=; b=kujlh78GTpQ3O3YfQsh/7IakN agQ1KkvYDt/+llTQyt4d5xLAm/bA4DXHsqiQGvN6eAAZqtKOztvhGGbOB8Qe+vrgiqO+7NHDBZXp3 xsmZggYUkc5xu80xveNPRsAMs924PxXSTuAQPHux5kLsG/yNDEcih9e1bXG+AV70TZ28kQtzz8zwB GIRnsrkv7FqagB5oGc7VJxuqKBBmrn64bld00iAh112Td+v7mjJU1u9p3499VugCtGT09BmsOc3+7 fFxzOBaoL2lmbsKKAk1h4LzvB1Zr9TTRqq5obS7gp3d4bT0IZgQZIeGAiZNc93RlQqLpKNwWwTtyg GLxaQX5Gg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1joSAv-0004tQ-CI; Thu, 25 Jun 2020 13:44:21 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1joSAr-0004qK-51 for linux-arm-kernel@lists.infradead.org; Thu, 25 Jun 2020 13:44:18 +0000 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 827B9338FB7BF2F083A7; Thu, 25 Jun 2020 21:44:10 +0800 (CST) Received: from A190218597.china.huawei.com (10.47.76.118) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 25 Jun 2020 21:44:01 +0800 From: Salil Mehta To: Subject: [PATCH RFC 3/4] arm64: kernel: Init cpu operations for all possible vcpus Date: Thu, 25 Jun 2020 14:37:56 +0100 Message-ID: <20200625133757.22332-4-salil.mehta@huawei.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20200625133757.22332-1-salil.mehta@huawei.com> References: <20200625133757.22332-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.76.118] X-CFilter-Loop: Reflected X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [45.249.212.35 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [45.249.212.35 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, peter.maydell@linaro.org, gshan@redhat.com, kvm@vger.kernel.org, mst@redhat.com, catalin.marinas@arm.com, linuxarm@huawei.com, linux-kernel@vger.kernel.org, will@kernel.org, Xiongfeng Wang , lorenzo.pieralisi@arm.com, maz@kernel.org, david@redhat.com, drjones@redhat.com, andre.przywara@arm.com, mehta.salil.lnk@gmail.com, richard.henderson@linaro.org, eric.auger@redhat.com, qemu-arm@nongnu.org, imammedo@redhat.com, Salil Mehta , christoffer.dall@arm.com, james.morse@arm.com, sudeep.holla@arm.com, pbonzini@redhat.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Currently, cpu-operations are only initialized for the cpus which already have logical cpuid to hwid assoication established. And this only happens for the cpus which are present during boot time. To support virtual cpu hotplug, we shall initialze the cpu-operations for all possible(present+disabled) vcpus. This means logical cpuid to hwid/mpidr association might not exists(i.e. might be INVALID_HWID) during init. Later, when the vcpu is actually hotplugged logical cpuid is allocated and associated with the hwid/mpidr. This patch does some refactoring to support above change. Signed-off-by: Salil Mehta Signed-off-by: Xiongfeng Wang --- arch/arm64/kernel/smp.c | 38 ++++++++++++++++---------------------- 1 file changed, 16 insertions(+), 22 deletions(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 864ccd3da419..63f31ea23e55 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -503,13 +503,16 @@ static int __init smp_cpu_setup(int cpu) const struct cpu_operations *ops; if (init_cpu_ops(cpu)) - return -ENODEV; + goto out; ops = get_cpu_ops(cpu); if (ops->cpu_init(cpu)) - return -ENODEV; + goto out; return 0; +out: + cpu_logical_map(cpu) = INVALID_HWID; + return -ENODEV; } static bool bootcpu_valid __initdata; @@ -547,7 +550,8 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); #else cpu_madt_gicc[total_cpu_count] = *processor; - set_cpu_possible(total_cpu_count, true); + if (!smp_cpu_setup(total_cpu_count)) + set_cpu_possible(total_cpu_count, true); disabled_cpu_count++; #endif return; @@ -591,8 +595,11 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) */ acpi_set_mailbox_entry(total_cpu_count, processor); - set_cpu_possible(total_cpu_count, true); - set_cpu_present(total_cpu_count, true); + if (!smp_cpu_setup(total_cpu_count)) { + set_cpu_possible(total_cpu_count, true); + set_cpu_present(total_cpu_count, true); + } + cpu_count++; } @@ -701,8 +708,10 @@ static void __init of_parse_and_init_cpus(void) early_map_cpu_to_node(cpu_count, of_node_to_nid(dn)); - set_cpu_possible(cpu_count, true); - set_cpu_present(cpu_count, true); + if (!smp_cpu_setup(cpu_count)) { + set_cpu_possible(cpu_count, true); + set_cpu_present(cpu_count, true); + } next: cpu_count++; } @@ -716,7 +725,6 @@ static void __init of_parse_and_init_cpus(void) void __init smp_init_cpus(void) { unsigned int total_cpu_count = disabled_cpu_count + cpu_count; - int i; if (acpi_disabled) of_parse_and_init_cpus(); @@ -731,20 +739,6 @@ void __init smp_init_cpus(void) pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); return; } - - /* - * We need to set the cpu_logical_map entries before enabling - * the cpus so that cpu processor description entries (DT cpu nodes - * and ACPI MADT entries) can be retrieved by matching the cpu hwid - * with entries in cpu_logical_map while initializing the cpus. - * If the cpu set-up fails, invalidate the cpu_logical_map entry. - */ - for (i = 1; i < nr_cpu_ids; i++) { - if (cpu_logical_map(i) != INVALID_HWID) { - if (smp_cpu_setup(i)) - cpu_logical_map(i) = INVALID_HWID; - } - } } void __init smp_prepare_cpus(unsigned int max_cpus)