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IronPort-SDR: FCIeI9nI6414nJ7ksSRxJS2d4awbwnDfmW5mcNChBuvks4bbmqF2IsOPpo6eXjXRwdRRxjSmaR KAoH4M0zfg3ll5n7w3zPaD7UkhezRadn/zdwKLcZrkUF9WPBU7R8GAeXu42Eq7B4uTJjQ16/F1 IMXoeQNi7vqXj69PGAHVeMMibjwiw2sBBJ6bYWEs4+lfWVUjszomyASpWoSXACRi3nlu/a8zkb 2lGs0UoRbWk8LIZ3cxRuzrKyo7uFG3+VJmiA5YeeVRQc9x16EJAbrRqaoPyF4auOXyJwg2/RpM 2zY= X-IronPort-AV: E=Sophos;i="5.75,304,1589266800"; d="scan'208";a="85979780" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 02 Jul 2020 03:14:40 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 2 Jul 2020 03:14:40 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 2 Jul 2020 03:14:17 -0700 From: Lars Povlsen To: Mark Brown , Peter Rosin , "Rob Herring" Subject: [PATCH v3 6/8] dt-bindings: microchip, sparx5-spi-mux: Add Sparx5 SPI mux driver bindings Date: Thu, 2 Jul 2020 12:13:29 +0200 Message-ID: <20200702101331.26375-7-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200702101331.26375-1-lars.povlsen@microchip.com> References: <20200702101331.26375-1-lars.povlsen@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200702_061441_682445_406842A8 X-CRM114-Status: GOOD ( 11.73 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [68.232.147.91 listed in wl.mailspike.net] -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.147.91 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Serge Semin , linux-spi@vger.kernel.org, Serge Semin , Lars Povlsen , Microchip Linux Driver Support , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The Microchip Sparx5 SPI controller has two bus segments, and use this mux to control the bus interface mapping for any chip selects. This decribes the bindings used to configure the mux driver. Signed-off-by: Lars Povlsen --- .../mux/microchip,sparx5-spi-mux.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml -- 2.27.0 diff --git a/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml b/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml new file mode 100644 index 0000000000000..b0ce3b15a69e5 --- /dev/null +++ b/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/microchip,sparx5-spi-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 SPI mux + +maintainers: + - Lars Povlsen + +description: | + The Microchip Sparx5 SPI controller has two bus segments. In order + to switch between the appropriate bus for any given SPI slave + (defined by a chip select), this mux driver is used. The device tree + node for the mux will define the bus mapping for any chip + selects. The default bus mapping for any chip select is "0", such + that only non-default mappings need to be explicitly defined. + +properties: + compatible: + enum: + - microchip,sparx5-spi-mux + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#mux-control-cells': + const: 0 + +required: + - compatible + +additionalProperties: false + +patternProperties: + "^mux@[0-9a-f]$": + type: object + + properties: + reg: + description: + Chip select to define bus mapping for. + minimum: 0 + maximum: 15 + + microchip,bus-interface: + description: + The bus interface to use for this chip select. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + required: + - reg + - microchip,bus-interface + +examples: + - | + mux: mux-controller { + compatible = "microchip,sparx5-spi-mux"; + #address-cells = <1>; + #size-cells = <0>; + #mux-control-cells = <0>; + mux@e { + reg = <14>; + microchip,bus-interface = <1>; + }; + };