From patchwork Thu Jul 2 20:16:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Nowicki X-Patchwork-Id: 11640377 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AE5DD739 for ; Thu, 2 Jul 2020 20:18:34 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 87BE420772 for ; Thu, 2 Jul 2020 20:18:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="i5ltrhiM"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=semihalf-com.20150623.gappssmtp.com header.i=@semihalf-com.20150623.gappssmtp.com header.b="NsMNCLtv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 87BE420772 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=semihalf.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=8bMDqta0/dGTvyckb7dAMz8vco9Dwc1anRRlWzdQz5A=; b=i5ltrhiMwuREzKVMMHtBwWiD9Y lmyzCbRxQ5q0e+Q05GILiGJPwWtu02UXcN33TSjT0NxUA8Ku4UuNKo8KBEofrx4j3rGQEBw0sCrt5 GHrd+eNhSV6Ocx8z73Y5bHi8iSs3cmm6Q8+BuBPGwyJF9Bhl0ZRNnF7UCO4dzFYSL2lA32lFojmNO g/yFgji5JRGugleew71+OV3Ip64/tQ2jv8QrXLF2OPpQFmrvkDRm5o4q7B1FM9DieLR+W8m6ibeMF Tn+tQeew2AxO4nmaihXl+cDVV+w9xrDh0ItQYsfLhmcTP6xmZiCLIl6K9VoxDlGlZv4QQ3w4NxP32 iAXxLpLg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jr5dr-00058a-Ma; Thu, 02 Jul 2020 20:17:07 +0000 Received: from mail-lj1-x244.google.com ([2a00:1450:4864:20::244]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jr5dm-00056K-6e for linux-arm-kernel@lists.infradead.org; Thu, 02 Jul 2020 20:17:03 +0000 Received: by mail-lj1-x244.google.com with SMTP id e4so33898275ljn.4 for ; Thu, 02 Jul 2020 13:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9HqU9qZ8LmsuIM9rC8wWt6FyyRyxinkgL6r/PQ1v140=; b=NsMNCLtvpw+rfbkzZ7WMHoUxkhwYpEr7ti2zDzD4RO214DSM61TASKnJ70FUtvL8Xe OPkb+gbm15X1yDJx8XxVSNyulMFihrw0kGMzp8vrp1BuuVpeJX/44bcILZU1krIWZ1ij TCU/iBWbRN7DpMH6Osw8VUjMetNmm0b7KEZZj4o1KCjJjNrY8KaBojlb9ezzxTtQVnmh ciCxQfncvCUnyTDyh/AyZkjjtzGGjrpW0bj/UIgKdP1x6X/BPSLWc/7Qb/0pwsUDF8WI pCfcE1Jy0ZYxCK29bhuFMsA3hjr0CQFi6Yq6smYXJZhNjvpLa4GTNN/vGt8GXvyzOIqP 7kRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9HqU9qZ8LmsuIM9rC8wWt6FyyRyxinkgL6r/PQ1v140=; b=NkfB8KkmKYEHL6zo4iogbaJnmU0H1PHPBRvTnEDCzs+SHVW2YMqZ4gWoIsBXGe0ME/ 5ys3wzqiboJf85kV0Ua03JRTBmGcs9QSGCP46APxFfXVbbc3F38R95HgPFVQuExB6JHs jhgp3wPsEeTpNprGhNZrcamM1A9kkyFJZ3TUx5CeXxCcJOsjNxs0BJ8UGAzobfgc1A0B iFdL+9NhMEp1orlhhgM5VgFiKR4QTmhfy7jL3W32Rj0if5l2bIZPvyPiPkeZL9lxZvfp 8LPRhxzA4O4dCk01p8rZ7VwTNJlbT9RgDgAibMPpsTrKNv6g8ozd6NGTdfqIEGxariLB KcnQ== X-Gm-Message-State: AOAM532kDW0Jzwii6lmWzVT5rJzzHTefU8jYYZE0HpmxMW5A8TLen92l J49KSvpVd3OlEvE2JUXihNNP8g== X-Google-Smtp-Source: ABdhPJxGJkhWxJ6CLztWNrISccJQIv1xdDY/rNe/lZBtJ1m/1dz/spNq4FMTtpQYU5jq8Ot1Y9n/tA== X-Received: by 2002:a2e:2c18:: with SMTP id s24mr10019389ljs.291.1593721020921; Thu, 02 Jul 2020 13:17:00 -0700 (PDT) Received: from localhost.localdomain ([83.68.95.66]) by smtp.gmail.com with ESMTPSA id y2sm3320372lji.8.2020.07.02.13.16.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2020 13:17:00 -0700 (PDT) From: Tomasz Nowicki To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, gregory.clement@bootlin.com, robh+dt@kernel.org, hannah@marvell.com Subject: [PATCH v3 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 Date: Thu, 2 Jul 2020 22:16:31 +0200 Message-Id: <20200702201633.22693-3-tn@semihalf.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200702201633.22693-1-tn@semihalf.com> References: <20200702201633.22693-1-tn@semihalf.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200702_161702_298670_D93BE6F3 X-CRM114-Status: GOOD ( 16.79 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:244 listed in] [list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, nadavh@marvell.com, iommu@lists.linux-foundation.org, Tomasz Nowicki , mw@semihalf.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Hanna Hawa Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to ARM SMMUv2 registers. Provide implementation relevant hooks: - split the writeq/readq to two accesses of writel/readl. - mask the MMU_IDR2.PTFSv8 fields to not use AArch64 format (but only AARCH32_L) since with AArch64 format 32 bits access is not supported. Note that separate writes/reads to 2 is not problem regards to atomicity, because the driver use the readq/writeq while initialize the SMMU, report for SMMU fault, and use spinlock in one case (iova_to_phys). Signed-off-by: Hanna Hawa Signed-off-by: Gregory CLEMENT Signed-off-by: Tomasz Nowicki --- Documentation/arm64/silicon-errata.rst | 3 ++ drivers/iommu/arm-smmu-impl.c | 52 ++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index 936cf2a59ca4..157214d3abe1 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -125,6 +125,9 @@ stable kernels. | Cavium | ThunderX2 Core | #219 | CAVIUM_TX2_ERRATUM_219 | +----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ +| Marvell | ARM-MMU-500 | #582743 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ ++----------------+-----------------+-----------------+-----------------------------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ diff --git a/drivers/iommu/arm-smmu-impl.c b/drivers/iommu/arm-smmu-impl.c index c75b9d957b70..c1fc5e1b8193 100644 --- a/drivers/iommu/arm-smmu-impl.c +++ b/drivers/iommu/arm-smmu-impl.c @@ -147,6 +147,53 @@ static const struct arm_smmu_impl arm_mmu500_impl = { .reset = arm_mmu500_reset, }; +static u64 mrvl_mmu500_readq(struct arm_smmu_device *smmu, int page, int off) +{ + u64 val; + + /* + * Marvell Armada-AP806 erratum #582743. + * Split all the readq to double readl + */ + val = (u64)readl_relaxed(arm_smmu_page(smmu, page) + off + 4) << 32; + val |= readl_relaxed(arm_smmu_page(smmu, page) + off); + + return val; +} + +static void mrvl_mmu500_writeq(struct arm_smmu_device *smmu, int page, int off, + u64 val) +{ + /* + * Marvell Armada-AP806 erratum #582743. + * Split all the writeq to double writel + */ + writel_relaxed(upper_32_bits(val), arm_smmu_page(smmu, page) + off + 4); + writel_relaxed(lower_32_bits(val), arm_smmu_page(smmu, page) + off); +} + +static u32 mrvl_mmu500_cfg_id2_fixup(u32 id) +{ + + /* + * Armada-AP806 erratum #582743. + * Hide the SMMU_IDR2.PTFSv8 fields to sidestep the AArch64 + * formats altogether and allow using 32 bits access on the + * interconnect. + */ + id &= ~(ARM_SMMU_ID2_PTFS_4K | ARM_SMMU_ID2_PTFS_16K | + ARM_SMMU_ID2_PTFS_64K); + + return id; +} + +static const struct arm_smmu_impl mrvl_mmu500_impl = { + .read_reg64 = mrvl_mmu500_readq, + .write_reg64 = mrvl_mmu500_writeq, + .cfg_id2_fixup = mrvl_mmu500_cfg_id2_fixup, + .reset = arm_mmu500_reset, +}; + struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) { @@ -160,6 +207,11 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) */ switch (smmu->model) { case ARM_MMU500: + if (of_device_is_compatible(smmu->dev->of_node, + "marvell,ap806-smmu-500")) { + smmu->impl = &mrvl_mmu500_impl; + return smmu; + } smmu->impl = &arm_mmu500_impl; break; case CAVIUM_SMMUV2: