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Fri, 10 Jul 2020 02:46:22 -0700 (PDT) From: Daniel Palmer To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 07/12] ARM: mstar: Add binding details for mstar,l3bridge Date: Fri, 10 Jul 2020 18:45:39 +0900 Message-Id: <20200710094544.430258-8-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200710094544.430258-1-daniel@0x0f.com> References: <20200710094544.430258-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200710_054626_341672_758770EE X-CRM114-Status: GOOD ( 15.76 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, arnd@arndb.de, Rob Herring , maz@kernel.org, Daniel Palmer , linux-kernel@vger.kernel.org, linux@armlinux.org.uk, robh+dt@kernel.org, w@1wt.eu, afaerber@suse.de Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This adds a YAML description of the l3bridge node needed by the platform code for the MStar/SigmaStar Armv7 SoCs. Signed-off-by: Daniel Palmer Reviewed-by: Rob Herring --- .../bindings/misc/mstar,l3bridge.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml diff --git a/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml b/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml new file mode 100644 index 000000000000..cb7fd1cdfb1a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/misc/mstar,l3bridge.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC l3bridge + +maintainers: + - Daniel Palmer + +description: | + MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface + between the CPU and memory. This means that before DMA capable + devices are allowed to run the pipeline must be flushed to ensure + everything is in memory. + + The l3bridge region contains registers that allow such a flush + to be triggered. + + This node is used by the platform code to find where the registers + are and install a barrier that triggers the required pipeline flush. + +properties: + compatible: + items: + - const: mstar,l3bridge + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + l3bridge: l3bridge@1f204400 { + compatible = "mstar,l3bridge"; + reg = <0x1f204400 0x200>; + };