| Message ID | 20200715064909.9161-2-andy.tang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2,v2] arm64: dts: ls1088a: add more thermal zone support | expand |
On Wed, Jul 15, 2020 at 12:25 PM <andy.tang@nxp.com> wrote: > > From: Yuantian Tang <andy.tang@nxp.com> > > There are 7 thermal zones in ls208xa soc. Add the other thermal zone > nodes to enable them. > > Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Reviewed-by: Amit Kucheria <amitk@kernel.org> > --- > v2: > - remove useless alert trip > - add cooling-map to core cluster zones. > > .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 141 ++++++++++++++++-- > 1 file changed, 132 insertions(+), 9 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi > index 41102dacc2e1..cc36c969dd9d 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi > @@ -79,20 +79,62 @@ > }; > > thermal-zones { > - cpu_thermal: cpu-thermal { > + ddr-controller1 { > polling-delay-passive = <1000>; > polling-delay = <5000>; > + thermal-sensors = <&tmu 1>; > > + trips { > + ddr-ctrler1-crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + }; > + > + ddr-controller2 { > + polling-delay-passive = <1000>; > + polling-delay = <5000>; > + thermal-sensors = <&tmu 2>; > + > + trips { > + ddr-ctrler2-crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + }; > + > + ddr-controller3 { > + polling-delay-passive = <1000>; > + polling-delay = <5000>; > + thermal-sensors = <&tmu 3>; > + > + trips { > + ddr-ctrler3-crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + }; > + > + core-cluster1 { > + polling-delay-passive = <1000>; > + polling-delay = <5000>; > thermal-sensors = <&tmu 4>; > > trips { > - cpu_alert: cpu-alert { > - temperature = <75000>; > + core_cluster1_alert: core-cluster1-alert { > + temperature = <85000>; > hysteresis = <2000>; > type = "passive"; > }; > - cpu_crit: cpu-crit { > - temperature = <85000>; > + > + core-cluster1-crit { > + temperature = <95000>; > hysteresis = <2000>; > type = "critical"; > }; > @@ -100,14 +142,95 @@ > > cooling-maps { > map0 { > - trip = <&cpu_alert>; > + trip = <&core_cluster1_alert>; > cooling-device = > <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > + > + core-cluster2 { > + polling-delay-passive = <1000>; > + polling-delay = <5000>; > + thermal-sensors = <&tmu 5>; > + > + trips { > + core_cluster2_alert: core-cluster2-alert { > + temperature = <85000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + core-cluster2-crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + > + cooling-maps { > + map0 { > + trip = <&core_cluster2_alert>; > + cooling-device = > <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > + > + core-cluster3 { > + polling-delay-passive = <1000>; > + polling-delay = <5000>; > + thermal-sensors = <&tmu 6>; > + > + trips { > + core_cluster3_alert: core-cluster3-alert { > + temperature = <85000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + core-cluster3-crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + > + cooling-maps { > + map0 { > + trip = <&core_cluster3_alert>; > + cooling-device = > <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > + > + core-cluster4 { > + polling-delay-passive = <1000>; > + polling-delay = <5000>; > + thermal-sensors = <&tmu 7>; > + > + trips { > + core_cluster4_alert: core-cluster4-alert { > + temperature = <85000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + core-cluster4-crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + > + cooling-maps { > + map0 { > + trip = <&core_cluster4_alert>; > + cooling-device = > <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > }; > -- > 2.17.1 >
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 41102dacc2e1..cc36c969dd9d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -79,20 +79,62 @@ }; thermal-zones { - cpu_thermal: cpu-thermal { + ddr-controller1 { polling-delay-passive = <1000>; polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + trips { + ddr-ctrler1-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + ddr-controller2 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 2>; + + trips { + ddr-ctrler2-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + ddr-controller3 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 3>; + + trips { + ddr-ctrler3-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + core-cluster1 { + polling-delay-passive = <1000>; + polling-delay = <5000>; thermal-sensors = <&tmu 4>; trips { - cpu_alert: cpu-alert { - temperature = <75000>; + core_cluster1_alert: core-cluster1-alert { + temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu-crit { - temperature = <85000>; + + core-cluster1-crit { + temperature = <95000>; hysteresis = <2000>; type = "critical"; }; @@ -100,14 +142,95 @@ cooling-maps { map0 { - trip = <&cpu_alert>; + trip = <&core_cluster1_alert>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + core-cluster2 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 5>; + + trips { + core_cluster2_alert: core-cluster2-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core-cluster2-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster2_alert>; + cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + core-cluster3 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 6>; + + trips { + core_cluster3_alert: core-cluster3-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core-cluster3-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster3_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + core-cluster4 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 7>; + + trips { + core_cluster4_alert: core-cluster4-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core-cluster4-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster4_alert>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; };