| Message ID | 20200715212227.26436-1-cphealy@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: dts: ZII: Disable HW Ethernet switch reset GPIO | expand |
On Wed, Jul 15, 2020 at 02:22:27PM -0700, Chris Healy wrote: > Disable Ethernet switch reset GPIO with ZII platforms that have it > enabled to sync up with existing ZII platforms that already have > it disabled. I do not follow it. The reset GPIO is part of hardware description. We shouldn't add or remove it for sake of sync-up with other platforms. Shawn > > Signed-off-by: Chris Healy <cphealy@gmail.com> > --- > arch/arm/boot/dts/vf610-zii-cfu1.dts | 2 -- > arch/arm/boot/dts/vf610-zii-spb4.dts | 2 -- > arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts | 2 -- > arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 2 -- > 4 files changed, 8 deletions(-) > > diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts > index ce1920c052fc..c2668230a4c0 100644 > --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts > +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts > @@ -170,7 +170,6 @@ > interrupts = <2 IRQ_TYPE_LEVEL_LOW>; > interrupt-controller; > #interrupt-cells = <2>; > - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; > > ports { > #address-cells = <1>; > @@ -354,7 +353,6 @@ > pinctrl_switch: switch-grp { > fsl,pins = < > VF610_PAD_PTB28__GPIO_98 0x3061 > - VF610_PAD_PTE2__GPIO_107 0x1042 > >; > }; > > diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts > index 55b4201e27f6..261317340189 100644 > --- a/arch/arm/boot/dts/vf610-zii-spb4.dts > +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts > @@ -127,7 +127,6 @@ > pinctrl-names = "default"; > reg = <0>; > eeprom-length = <65536>; > - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; > interrupt-parent = <&gpio3>; > interrupts = <2 IRQ_TYPE_LEVEL_LOW>; > interrupt-controller; > @@ -312,7 +311,6 @@ > > pinctrl_gpio_switch0: pinctrl-gpio-switch0 { > fsl,pins = < > - VF610_PAD_PTE2__GPIO_107 0x31c2 > VF610_PAD_PTB28__GPIO_98 0x219d > >; > }; > diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts > index a6c22a79779e..e37b9643269b 100644 > --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts > +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts > @@ -113,7 +113,6 @@ > pinctrl-names = "default"; > reg = <0>; > eeprom-length = <65536>; > - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; > interrupt-parent = <&gpio3>; > interrupts = <2 IRQ_TYPE_LEVEL_LOW>; > interrupt-controller; > @@ -288,7 +287,6 @@ > > pinctrl_gpio_switch0: pinctrl-gpio-switch0 { > fsl,pins = < > - VF610_PAD_PTE2__GPIO_107 0x31c2 > VF610_PAD_PTB28__GPIO_98 0x219d > >; > }; > diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts > index 3d05c894bdc0..b3d6d4b9fa9c 100644 > --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts > +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts > @@ -141,7 +141,6 @@ > pinctrl-names = "default"; > reg = <0>; > eeprom-length = <65536>; > - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; > interrupt-parent = <&gpio3>; > interrupts = <2 IRQ_TYPE_LEVEL_LOW>; > interrupt-controller; > @@ -319,7 +318,6 @@ > > pinctrl_gpio_switch0: pinctrl-gpio-switch0 { > fsl,pins = < > - VF610_PAD_PTE2__GPIO_107 0x31c2 > VF610_PAD_PTB28__GPIO_98 0x219d > >; > }; > -- > 2.21.3 >
On Sun, Jul 19, 2020 at 8:15 PM Shawn Guo <shawnguo@kernel.org> wrote: > > On Wed, Jul 15, 2020 at 02:22:27PM -0700, Chris Healy wrote: > > Disable Ethernet switch reset GPIO with ZII platforms that have it > > enabled to sync up with existing ZII platforms that already have > > it disabled. > > I do not follow it. The reset GPIO is part of hardware description. We > shouldn't add or remove it for sake of sync-up with other platforms. I see that my description is not very good. What I should have said is that we don't want to use the HW reset GPIO as it results in things being done that we do not want done. Specifically, when the switch is hit with the HW reset GPIO, it results in the switch's copper PHYs being HW reset which we want to avoid as this results in unnecessary network downtime on a soft reboot of the processor. With the HW reset GPIO not in the devicetree description, the switch driver resorts to doing a SW reset which resets the switch core but not the switch's copper PHYs. This results in a much shorter network downtime on a soft reboot of the processor. I can do a v2 of the patch with the description updated if you think it would be appropriate. > > Shawn > > > > > Signed-off-by: Chris Healy <cphealy@gmail.com> > > --- > > arch/arm/boot/dts/vf610-zii-cfu1.dts | 2 -- > > arch/arm/boot/dts/vf610-zii-spb4.dts | 2 -- > > arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts | 2 -- > > arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 2 -- > > 4 files changed, 8 deletions(-) > > > > diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts > > index ce1920c052fc..c2668230a4c0 100644 > > --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts > > +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts > > @@ -170,7 +170,6 @@ > > interrupts = <2 IRQ_TYPE_LEVEL_LOW>; > > interrupt-controller; > > #interrupt-cells = <2>; > > - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; > > > > ports { > > #address-cells = <1>; > > @@ -354,7 +353,6 @@ > > pinctrl_switch: switch-grp { > > fsl,pins = < > > VF610_PAD_PTB28__GPIO_98 0x3061 > > - VF610_PAD_PTE2__GPIO_107 0x1042 > > >; > > }; > > > > diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts > > index 55b4201e27f6..261317340189 100644 > > --- a/arch/arm/boot/dts/vf610-zii-spb4.dts > > +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts > > @@ -127,7 +127,6 @@ > > pinctrl-names = "default"; > > reg = <0>; > > eeprom-length = <65536>; > > - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; > > interrupt-parent = <&gpio3>; > > interrupts = <2 IRQ_TYPE_LEVEL_LOW>; > > interrupt-controller; > > @@ -312,7 +311,6 @@ > > > > pinctrl_gpio_switch0: pinctrl-gpio-switch0 { > > fsl,pins = < > > - VF610_PAD_PTE2__GPIO_107 0x31c2 > > VF610_PAD_PTB28__GPIO_98 0x219d > > >; > > }; > > diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts > > index a6c22a79779e..e37b9643269b 100644 > > --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts > > +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts > > @@ -113,7 +113,6 @@ > > pinctrl-names = "default"; > > reg = <0>; > > eeprom-length = <65536>; > > - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; > > interrupt-parent = <&gpio3>; > > interrupts = <2 IRQ_TYPE_LEVEL_LOW>; > > interrupt-controller; > > @@ -288,7 +287,6 @@ > > > > pinctrl_gpio_switch0: pinctrl-gpio-switch0 { > > fsl,pins = < > > - VF610_PAD_PTE2__GPIO_107 0x31c2 > > VF610_PAD_PTB28__GPIO_98 0x219d > > >; > > }; > > diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts > > index 3d05c894bdc0..b3d6d4b9fa9c 100644 > > --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts > > +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts > > @@ -141,7 +141,6 @@ > > pinctrl-names = "default"; > > reg = <0>; > > eeprom-length = <65536>; > > - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; > > interrupt-parent = <&gpio3>; > > interrupts = <2 IRQ_TYPE_LEVEL_LOW>; > > interrupt-controller; > > @@ -319,7 +318,6 @@ > > > > pinctrl_gpio_switch0: pinctrl-gpio-switch0 { > > fsl,pins = < > > - VF610_PAD_PTE2__GPIO_107 0x31c2 > > VF610_PAD_PTB28__GPIO_98 0x219d > > >; > > }; > > -- > > 2.21.3 > >
diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index ce1920c052fc..c2668230a4c0 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -170,7 +170,6 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <2>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; ports { #address-cells = <1>; @@ -354,7 +353,6 @@ pinctrl_switch: switch-grp { fsl,pins = < VF610_PAD_PTB28__GPIO_98 0x3061 - VF610_PAD_PTE2__GPIO_107 0x1042 >; }; diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts index 55b4201e27f6..261317340189 100644 --- a/arch/arm/boot/dts/vf610-zii-spb4.dts +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts @@ -127,7 +127,6 @@ pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -312,7 +311,6 @@ pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts index a6c22a79779e..e37b9643269b 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -113,7 +113,6 @@ pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -288,7 +287,6 @@ pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 3d05c894bdc0..b3d6d4b9fa9c 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -141,7 +141,6 @@ pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -319,7 +318,6 @@ pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; };
Disable Ethernet switch reset GPIO with ZII platforms that have it enabled to sync up with existing ZII platforms that already have it disabled. Signed-off-by: Chris Healy <cphealy@gmail.com> --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 2 -- arch/arm/boot/dts/vf610-zii-spb4.dts | 2 -- arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts | 2 -- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 2 -- 4 files changed, 8 deletions(-)