From patchwork Wed Jul 22 17:20:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 11679023 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 255181510 for ; Wed, 22 Jul 2020 17:24:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B614F207BB for ; Wed, 22 Jul 2020 17:24:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="s+RekRfP" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B614F207BB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=D1BXMD7T0j0OdAn2seTBAd3/VAdqP0yBRk1B+Hqpxpc=; b=s+RekRfPyBqrVUkm3jBwtx7O8 XJ6adMabnUg8IRSKN81Q6KWMaHyQ7Qkv0LFIq2IkphiH8W3mz+dTw63rDgi0hfMC+WKVjPeXJz45Y 471NU2Py3Ri8YXnN0qFoybACEcase/6mtsNCGwjHBE1RvnOxJLjhZUJtPuHUqFzyaBHBceXI7Daat N3rbcCA/4h2ZaZXOv6nRyNtvwVLykVqREMh/cWTCWV3yIXvvaZFyrvv+qLaqdlw2Lzw5UHgsLJ9YB j48jjq1E5LEfipxnSrSli8NwMhRiO39d2Oo9ecaOaa7YJZCrAiaRgmof0QWRx/XfK1GFiptn7t2fZ v72/96TUQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jyIRD-0007yN-6S; Wed, 22 Jul 2020 17:21:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jyIQW-0007gn-6s for linux-arm-kernel@lists.infradead.org; Wed, 22 Jul 2020 17:21:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E3A9F31B; Wed, 22 Jul 2020 10:21:07 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0A3AA3F66F; Wed, 22 Jul 2020 10:21:06 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 11/14] coresight: etm4x: Detect system register access support Date: Wed, 22 Jul 2020 18:20:37 +0100 Message-Id: <20200722172040.1299289-12-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200722172040.1299289-1-suzuki.poulose@arm.com> References: <20200722172040.1299289-1-suzuki.poulose@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200722_132108_382709_E544AA56 X-CRM114-Status: GOOD ( 17.64 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: coresight@lists.linaro.org, Suzuki K Poulose , linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org, mike.leach@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Check if the etm4x supports system register access and use it instead of the memory mapped IO. We need to detect that : a) The CPU implements system register access to the Trace unit AND b) The trace unit is an ETMv4.x component. Cc: Mathieu Poirier Cc: Mike Leach Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etm4x.c | 76 +++++++++++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 16 ++++ 2 files changed, 78 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 776a59f62710..831206f7f306 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -1507,9 +1508,43 @@ static void etm4_pm_clear(void) } } +static inline bool trace_unit_is_etmv4(u32 devarch) +{ + return (devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH; +} + +static void etm4_check_sysreg_access(void *arg) +{ + bool *status = arg; + u32 devarch; + + if (!arch_cpu_supports_sysreg_trace()) { + *status = false; + return; + } + + devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH); + if (!trace_unit_is_etmv4(devarch)) { + *status = false; + return; + } + + *status = true; +} + +static bool etm4_cpu_supports_sysreg(int cpu) +{ + bool sys_reg_support = false; + + smp_call_function_single(cpu, etm4_check_sysreg_access, &sys_reg_support, 1); + + return sys_reg_support; +} + static int etm4_probe(struct amba_device *adev, const struct amba_id *id) { - int ret; + int ret, cpu; + bool sys_reg = false; void __iomem *base; struct device *dev = &adev->dev; struct coresight_platform_data *pdata = NULL; @@ -1517,10 +1552,17 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) struct resource *res = &adev->res; struct coresight_desc desc = { 0 }; + cpu = coresight_get_cpu(dev); + if (cpu < 0 || !cpu_online(cpu)) + return -EPROBE_DEFER; + + sys_reg = etm4_cpu_supports_sysreg(cpu); + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; + drvdata->cpu = cpu; dev_set_drvdata(dev, drvdata); if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) @@ -1537,26 +1579,30 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) drvdata->skip_power_up = true; - /* Validity for the resource is already checked by the AMBA core */ - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - - drvdata->base = base; - desc.access.base = base; + if (sys_reg) { + desc.access = (struct csdev_access){ + .no_iomem = true, + .read = etm4x_sysreg_read, + .write = etm4x_sysreg_write, + }; + } else { + /* Validity for the resource is already checked by the AMBA core */ + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + drvdata->base = base; + desc.access.base = base; + } spin_lock_init(&drvdata->spinlock); - drvdata->cpu = coresight_get_cpu(dev); - if (drvdata->cpu < 0) - return drvdata->cpu; - desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu); if (!desc.name) return -ENOMEM; cpus_read_lock(); - etmdrvdata[drvdata->cpu] = drvdata; + etmdrvdata[cpu] = drvdata; if (smp_call_function_single(drvdata->cpu, etm4_init_arch_data, &desc.access, 1)) @@ -1607,6 +1653,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n", drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf); + if (sys_reg) + dev_info(&drvdata->csdev->dev, "Using system register accesses\n"); if (boot_enable) { coresight_enable(drvdata->csdev); @@ -1616,7 +1664,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return 0; err_arch_supported: - etmdrvdata[drvdata->cpu] = NULL; + etmdrvdata[cpu] = NULL; etm4_pm_clear(); return ret; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index ab3d1c195387..86fdcbafc895 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -152,6 +152,13 @@ #define write_etm4x_sysreg_const_offset(val, offset) \ WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset)) +static inline bool arch_cpu_supports_sysreg_trace(void) +{ + u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); + + return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0; +} + #elif defined(CONFIG_ARM) #include @@ -172,6 +179,15 @@ #define write_etm4x_sysreg_const_offset(val, offset) \ WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset)) +#define ID_DFR0_CopTrc_SHIFT 12 +static inline bool arch_cpu_supports_sysreg_trace(void) +{ + u32 dfr0; + + asm volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (dfr0)); + + return ((dfr0 >> ID_DFR0_CopTrc_SHIFT) & 0xfUL) > 0; +} #endif #define CASE_READ(res, x) \