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Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 20 ++++++++++++ .../arm64/boot/dts/microchip/sparx5_nand.dtsi | 31 +++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 14 +++++++++ .../boot/dts/microchip/sparx5_pcb134.dts | 1 + .../boot/dts/microchip/sparx5_pcb135.dts | 1 + 5 files changed, 67 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/sparx5_nand.dtsi diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 2169746703dfb..8e9e3ed872496 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -212,6 +212,26 @@ gpio: pinctrl@6110101e0 { interrupts = ; #interrupt-cells = <2>; + cs1_pins: cs1-pins { + pins = "GPIO_16"; + function = "si"; + }; + + cs2_pins: cs2-pins { + pins = "GPIO_17"; + function = "si"; + }; + + cs3_pins: cs3-pins { + pins = "GPIO_18"; + function = "si"; + }; + + si2_pins: si2-pins { + pins = "GPIO_39", "GPIO_40", "GPIO_41"; + function = "si2"; + }; + uart_pins: uart-pins { pins = "GPIO_10", "GPIO_11"; function = "uart"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi new file mode 100644 index 0000000000000..03f107e427d70 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +&gpio { + cs14_pins: cs14-pins { + pins = "GPIO_44"; + function = "si"; + }; +}; + +&spi0 { + pinctrl-0 = <&si2_pins>; + pinctrl-names = "default"; + spi@e { + compatible = "spi-mux"; + mux-controls = <&mux>; + #address-cells = <1>; + #size-cells = <0>; + reg = <14>; /* CS14 */ + spi-flash@6 { + compatible = "spi-nand"; + pinctrl-0 = <&cs14_pins>; + pinctrl-names = "default"; + reg = <0x6>; /* SPI2 */ + spi-max-frequency = <42000000>; + rx-sample-delay-ns = <7>; /* Tune for speed */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index c1eb1d661174d..6b2da7c7520cc 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -53,6 +53,20 @@ spi-flash@9 { reg = <0x9>; /* SPI */ }; }; + spi@1 { + compatible = "spi-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* CS1 */ + spi-flash@9 { + compatible = "spi-nand"; + pinctrl-0 = <&cs1_pins>; + pinctrl-names = "default"; + spi-max-frequency = <8000000>; + reg = <0x9>; /* SPI */ + }; + }; }; &i2c1 { diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts index feee4e99ff57c..45ca1af7e8500 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "sparx5_pcb134_board.dtsi" +#include "sparx5_nand.dtsi" / { model = "Sparx5 PCB134 Reference Board (NAND)"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts index 20e409a9be196..647cdb38b1130 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "sparx5_pcb135_board.dtsi" +#include "sparx5_nand.dtsi" / { model = "Sparx5 PCB135 Reference Board (NAND)";