@@ -137,13 +137,6 @@ config S3C2410_IOTIMING
Internal node to select io timing code that is common to the s3c2410
and s3c2440/s3c2442 cpu frequency support.
-config S3C2410_CPUFREQ_UTILS
- bool
- depends on ARM_S3C24XX_CPUFREQ
- help
- Internal node to select timing code that is common to the s3c2410
- and s3c2440/s3c244 cpu frequency support.
-
# cpu frequency support common to s3c2412, s3c2413 and s3c2442
config S3C2412_IOTIMING
@@ -38,7 +38,7 @@ obj-$(CONFIG_PM_SLEEP) += irq-pm.o sleep.o
# common code
-obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
+obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += cpufreq-utils.o
obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o
@@ -60,3 +60,35 @@ void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
if (!IS_ERR(cfg->mpll))
clk_set_rate(cfg->mpll, cfg->pll.frequency);
}
+
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
+u32 s3c2440_read_camdivn(void)
+{
+ return __raw_readl(S3C2440_CAMDIVN);
+}
+
+void s3c2440_write_camdivn(u32 camdiv)
+{
+ __raw_writel(camdiv, S3C2440_CAMDIVN);
+}
+#endif
+
+u32 s3c24xx_read_clkdivn(void)
+{
+ return __raw_readl(S3C2410_CLKDIVN);
+}
+
+void s3c24xx_write_clkdivn(u32 clkdiv)
+{
+ __raw_writel(clkdiv, S3C2410_CLKDIVN);
+}
+
+u32 s3c24xx_read_mpllcon(void)
+{
+ return __raw_readl(S3C2410_MPLLCON);
+}
+
+void s3c24xx_write_locktime(u32 locktime)
+{
+ return __raw_writel(locktime, S3C2410_LOCKTIME);
+}
@@ -196,7 +196,6 @@ config ARM_S3C24XX_CPUFREQ_DEBUGFS
config ARM_S3C2410_CPUFREQ
bool
depends on ARM_S3C24XX_CPUFREQ && CPU_S3C2410
- select S3C2410_CPUFREQ_UTILS
help
CPU Frequency scaling support for S3C2410
@@ -233,7 +232,6 @@ config ARM_S3C2416_CPUFREQ_VCORESCALE
config ARM_S3C2440_CPUFREQ
bool "S3C2440/S3C2442 CPU Frequency scaling support"
depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2440 || CPU_S3C2442)
- select S3C2410_CPUFREQ_UTILS
default y
help
CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
@@ -22,12 +22,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/map.h>
-
-#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
-
-#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
-
#define S3C2410_CLKDIVN_PDIVN (1<<0)
#define S3C2410_CLKDIVN_HDIVN (1<<1)
@@ -43,7 +37,7 @@ static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
if (cfg->divs.p_divisor != cfg->divs.h_divisor)
clkdiv |= S3C2410_CLKDIVN_PDIVN;
- __raw_writel(clkdiv, S3C2410_CLKDIVN);
+ s3c24xx_write_clkdivn(clkdiv);
}
static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
@@ -25,12 +25,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/map.h>
-
-#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
-
-#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
-
#define S3C2412_CLKDIVN_PDIVN (1<<2)
#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
#define S3C2412_CLKDIVN_ARMDIVN (1<<3)
@@ -132,7 +126,7 @@ static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
unsigned long clkdiv;
unsigned long olddiv;
- olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
+ olddiv = clkdiv = s3c24xx_read_clkdivn();
/* clear off current clock info */
@@ -149,7 +143,7 @@ static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
clkdiv |= S3C2412_CLKDIVN_PDIVN;
s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
- __raw_writel(clkdiv, S3C2410_CLKDIVN);
+ s3c24xx_write_clkdivn(clkdiv);
clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
}
@@ -26,12 +26,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/map.h>
-
-#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
-#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
-#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
-
#define S3C2440_CLKDIVN_PDIVN (1<<0)
#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
@@ -162,8 +156,8 @@ static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
s3c_freq_dbg("%s: divisors: h=%d, p=%d\n", __func__,
cfg->divs.h_divisor, cfg->divs.p_divisor);
- clkdiv = __raw_readl(S3C2410_CLKDIVN);
- camdiv = __raw_readl(S3C2440_CAMDIVN);
+ clkdiv = s3c24xx_read_clkdivn();
+ camdiv = s3c2440_read_camdivn();
clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
camdiv &= ~CAMDIVN_HCLK_HALF;
@@ -203,11 +197,11 @@ static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
* then make a short delay and remove the hclk halving if necessary.
*/
- __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
- __raw_writel(clkdiv, S3C2410_CLKDIVN);
+ s3c2440_write_camdivn(camdiv | CAMDIVN_HCLK_HALF);
+ s3c24xx_write_clkdivn(clkdiv);
ndelay(20);
- __raw_writel(camdiv, S3C2440_CAMDIVN);
+ s3c2440_write_camdivn(camdiv);
clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
}
@@ -27,13 +27,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/map.h>
-
/* note, cpufreq support deals in kHz, no Hz */
-#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
-#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
-#define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
-
static struct cpufreq_driver s3c24xx_driver;
static struct s3c_cpufreq_config cpu_cur;
static struct s3c_iotimings s3c24xx_iotiming;
@@ -70,7 +64,7 @@ static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
- cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON);
+ cfg->pll.driver_data = s3c24xx_read_mpllcon();
cfg->pll.frequency = fclk;
cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
@@ -388,7 +382,7 @@ static unsigned int suspend_freq;
static int s3c_cpufreq_suspend(struct cpufreq_policy *policy)
{
suspend_pll.frequency = clk_get_rate(_clk_mpll);
- suspend_pll.driver_data = __raw_readl(S3C2410_MPLLCON);
+ suspend_pll.driver_data = s3c24xx_read_mpllcon();
suspend_freq = clk_get_rate(clk_arm);
return 0;
@@ -549,7 +543,7 @@ static void s3c_cpufreq_update_loctkime(void)
val |= calc_locktime(rate, cpu_cur.info->locktime_m);
pr_info("%s: new locktime is 0x%08x\n", __func__, val);
- __raw_writel(val, S3C2410_LOCKTIME);
+ s3c24xx_write_locktime(val);
}
static int s3c_cpufreq_build_freq(void)
@@ -289,4 +289,11 @@ static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
return index + 1;
}
+u32 s3c2440_read_camdivn(void);
+void s3c2440_write_camdivn(u32 camdiv);
+u32 s3c24xx_read_clkdivn(void);
+void s3c24xx_write_clkdivn(u32 clkdiv);
+u32 s3c24xx_read_mpllcon(void);
+void s3c24xx_write_locktime(u32 locktime);
+
#endif