| Message ID | 20200825131049.1277596-1-jernej.skrabec@siol.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL | expand |
On Tue, Aug 25, 2020 at 03:10:49PM +0200, Jernej Skrabec wrote: > Audio cores need specific clock rates which can't be simply obtained by > adjusting integer multipliers and dividers. HW for such cases supports > delta-sigma modulation which enables fractional multipliers. > > Port H3 delta-sigma table to R40. They have identical audio PLLs. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Applied, thanks! Maxime
On Tue, Aug 25, 2020 at 9:11 PM Jernej Skrabec <jernej.skrabec@siol.net> wrote: > > Audio cores need specific clock rates which can't be simply obtained by > adjusting integer multipliers and dividers. HW for such cases supports > delta-sigma modulation which enables fractional multipliers. > > Port H3 delta-sigma table to R40. They have identical audio PLLs. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > --- > drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 37 ++++++++++++++++++---------- > 1 file changed, 24 insertions(+), 13 deletions(-) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > index 23bfe1d12f21..84153418453f 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > @@ -45,18 +45,29 @@ static struct ccu_nkmp pll_cpu_clk = { > * the base (2x, 4x and 8x), and one variable divider (the one true > * pll audio). > * > - * We don't have any need for the variable divider for now, so we just > - * hardcode it to match with the clock names > + * With sigma-delta modulation for fractional-N on the audio PLL, > + * we have to use specific dividers. This means the variable divider > + * can no longer be used, as the audio codec requests the exact clock > + * rates we support through this mechanism. So we now hard code the > + * variable divider to 1. This means the clock rates will no longer > + * match the clock names. > */ > #define SUN8I_R40_PLL_AUDIO_REG 0x008 > > -static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", > - "osc24M", 0x008, > - 8, 7, /* N */ > - 0, 5, /* M */ > - BIT(31), /* gate */ > - BIT(28), /* lock */ > - CLK_SET_RATE_UNGATE); > +static struct ccu_sdm_setting pll_audio_sdm_table[] = { > + { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, > + { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, The user manual has an additional requirement: 3 <= N/M <= 21. Though it then says 72 <= 24*N/P <= 504. Not sure which one is right... Did you run into any glitches or audio distortions? ChenYu
Dne torek, 25. avgust 2020 ob 16:46:31 CEST je Chen-Yu Tsai napisal(a): > On Tue, Aug 25, 2020 at 9:11 PM Jernej Skrabec <jernej.skrabec@siol.net> wrote: > > Audio cores need specific clock rates which can't be simply obtained by > > adjusting integer multipliers and dividers. HW for such cases supports > > delta-sigma modulation which enables fractional multipliers. > > > > Port H3 delta-sigma table to R40. They have identical audio PLLs. > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > --- > > > > drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 37 ++++++++++++++++++---------- > > 1 file changed, 24 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > > b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c index 23bfe1d12f21..84153418453f > > 100644 > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > > @@ -45,18 +45,29 @@ static struct ccu_nkmp pll_cpu_clk = { > > > > * the base (2x, 4x and 8x), and one variable divider (the one true > > * pll audio). > > * > > > > - * We don't have any need for the variable divider for now, so we just > > - * hardcode it to match with the clock names > > + * With sigma-delta modulation for fractional-N on the audio PLL, > > + * we have to use specific dividers. This means the variable divider > > + * can no longer be used, as the audio codec requests the exact clock > > + * rates we support through this mechanism. So we now hard code the > > + * variable divider to 1. This means the clock rates will no longer > > + * match the clock names. > > > > */ > > > > #define SUN8I_R40_PLL_AUDIO_REG 0x008 > > > > -static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", > > - "osc24M", 0x008, > > - 8, 7, /* N */ > > - 0, 5, /* M */ > > - BIT(31), /* gate */ > > - BIT(28), /* lock */ > > - CLK_SET_RATE_UNGATE); > > +static struct ccu_sdm_setting pll_audio_sdm_table[] = { > > + { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, > > + { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, > > The user manual has an additional requirement: 3 <= N/M <= 21. > Though it then says 72 <= 24*N/P <= 504. Not sure which one is > right... > > Did you run into any glitches or audio distortions? No, I tested HDMI audio and it seems to work fine. BSP driver also uses those values: https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/drivers/ clk/sunxi/clk-sun8iw11.c#L160 Best regards, Jernej
On Wed, Aug 26, 2020 at 12:45 AM Jernej Škrabec <jernej.skrabec@siol.net> wrote: > > Dne torek, 25. avgust 2020 ob 16:46:31 CEST je Chen-Yu Tsai napisal(a): > > On Tue, Aug 25, 2020 at 9:11 PM Jernej Skrabec <jernej.skrabec@siol.net> > wrote: > > > Audio cores need specific clock rates which can't be simply obtained by > > > adjusting integer multipliers and dividers. HW for such cases supports > > > delta-sigma modulation which enables fractional multipliers. > > > > > > Port H3 delta-sigma table to R40. They have identical audio PLLs. > > > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > > --- > > > > > > drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 37 ++++++++++++++++++---------- > > > 1 file changed, 24 insertions(+), 13 deletions(-) > > > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > > > b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c index 23bfe1d12f21..84153418453f > > > 100644 > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > > > @@ -45,18 +45,29 @@ static struct ccu_nkmp pll_cpu_clk = { > > > > > > * the base (2x, 4x and 8x), and one variable divider (the one true > > > * pll audio). > > > * > > > > > > - * We don't have any need for the variable divider for now, so we just > > > - * hardcode it to match with the clock names > > > + * With sigma-delta modulation for fractional-N on the audio PLL, > > > + * we have to use specific dividers. This means the variable divider > > > + * can no longer be used, as the audio codec requests the exact clock > > > + * rates we support through this mechanism. So we now hard code the > > > + * variable divider to 1. This means the clock rates will no longer > > > + * match the clock names. > > > > > > */ > > > > > > #define SUN8I_R40_PLL_AUDIO_REG 0x008 > > > > > > -static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", > > > - "osc24M", 0x008, > > > - 8, 7, /* N */ > > > - 0, 5, /* M */ > > > - BIT(31), /* gate */ > > > - BIT(28), /* lock */ > > > - CLK_SET_RATE_UNGATE); > > > +static struct ccu_sdm_setting pll_audio_sdm_table[] = { > > > + { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, > > > + { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, > > > > The user manual has an additional requirement: 3 <= N/M <= 21. > > Though it then says 72 <= 24*N/P <= 504. Not sure which one is > > right... > > > > Did you run into any glitches or audio distortions? > > No, I tested HDMI audio and it seems to work fine. > > BSP driver also uses those values: > https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/drivers/ > clk/sunxi/clk-sun8iw11.c#L160 Sounds good. Thanks.
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c index 23bfe1d12f21..84153418453f 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c @@ -45,18 +45,29 @@ static struct ccu_nkmp pll_cpu_clk = { * the base (2x, 4x and 8x), and one variable divider (the one true * pll audio). * - * We don't have any need for the variable divider for now, so we just - * hardcode it to match with the clock names + * With sigma-delta modulation for fractional-N on the audio PLL, + * we have to use specific dividers. This means the variable divider + * can no longer be used, as the audio codec requests the exact clock + * rates we support through this mechanism. So we now hard code the + * variable divider to 1. This means the clock rates will no longer + * match the clock names. */ #define SUN8I_R40_PLL_AUDIO_REG 0x008 -static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", - "osc24M", 0x008, - 8, 7, /* N */ - 0, 5, /* M */ - BIT(31), /* gate */ - BIT(28), /* lock */ - CLK_SET_RATE_UNGATE); +static struct ccu_sdm_setting pll_audio_sdm_table[] = { + { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, + { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, +}; + +static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7, /* N */ + 0, 5, /* M */ + pll_audio_sdm_table, BIT(24), + 0x284, BIT(31), + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0", "osc24M", 0x0010, @@ -952,10 +963,10 @@ static const struct clk_hw *clk_parent_pll_audio[] = { &pll_audio_base_clk.common.hw }; -/* We hardcode the divider to 4 for now */ +/* We hardcode the divider to 1 for now */ static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", clk_parent_pll_audio, - 4, 1, CLK_SET_RATE_PARENT); + 1, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", clk_parent_pll_audio, 2, 1, CLK_SET_RATE_PARENT); @@ -1307,10 +1318,10 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev) if (IS_ERR(reg)) return PTR_ERR(reg); - /* Force the PLL-Audio-1x divider to 4 */ + /* Force the PLL-Audio-1x divider to 1 */ val = readl(reg + SUN8I_R40_PLL_AUDIO_REG); val &= ~GENMASK(19, 16); - writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG); + writel(val | (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG); /* Force PLL-MIPI to MIPI mode */ val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
Audio cores need specific clock rates which can't be simply obtained by adjusting integer multipliers and dividers. HW for such cases supports delta-sigma modulation which enables fractional multipliers. Port H3 delta-sigma table to R40. They have identical audio PLLs. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> --- drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 37 ++++++++++++++++++---------- 1 file changed, 24 insertions(+), 13 deletions(-)