From patchwork Fri Aug 28 14:20:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11742943 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 02D39913 for ; Fri, 28 Aug 2020 14:22:47 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CBE6C2054F for ; Fri, 28 Aug 2020 14:22:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="J85Dbmr2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CBE6C2054F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=iw4qcW2BGIERC51lx7pwIDnIXKYvf8smaX8f3dwCGf0=; b=J85Dbmr2IOSJPsi5UhNSQm5g0W ugDAuy/cRVwO8HK2zwysLX2Dmmm97Ukaktm2lfUCnIoyY4IZjx91oDKA2r3gu1ARHLMEd70yi6eko +QeK7vzne7YhNTD4R4wA5x64Em3c5VovgZbn/Bzw0AWN61RayXOi7FxxbmSMVo6noK4QE8YsUXtb9 3RpvQ0cz0sctHfjD2HXfjdUhn9ucO6qtOpX0yV8qNgvrO/JLZj83cTU01aSi3xbpJlpBuijP7x1wu TgzfRuWDNJt6D/ppfwbTw/VR6SqmiPyaqq2dbumrYj7yG39qcsoXdXpVRrNRLK+VeDO2DeOYKtSxG saisgqQA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kBfF8-0007CE-0J; Fri, 28 Aug 2020 14:20:38 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kBfF1-0007AA-Ig for linux-arm-kernel@lists.infradead.org; Fri, 28 Aug 2020 14:20:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8CF79D6E; Fri, 28 Aug 2020 07:20:30 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.195.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7855D3F71F; Fri, 28 Aug 2020 07:20:28 -0700 (PDT) From: Andre Przywara To: Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v2 1/6] dt-bindings: timers: sp-804: Convert to json-schema Date: Fri, 28 Aug 2020 15:20:13 +0100 Message-Id: <20200828142018.43298-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200828142018.43298-1-andre.przywara@arm.com> References: <20200828142018.43298-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200828_102031_774101_10B41E00 X-CRM114-Status: GOOD ( 24.29 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lorenzo Pieralisi , Scott Branden , Ray Jui , Chanho Min , Daniel Lezcano , Liviu Dudau , linux-kernel@vger.kernel.org, Wei Xu , Florian Fainelli , Haojian Zhuang , Sudeep Holla , Thomas Gleixner , Linus Walleij , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This converts the DT binding documentation for the ARM SP-804 timer IP over to json-schema. Most properties are just carried over, the clocks property requirement (either one or three clocks) is now formalised and enforced. As the former binding didn't specify clock-names, and there is no common name used by the existing DTs, I refrained from adding them in detail (just allowing the property). The requirement for the APB clock is enforced by the primecell binding already. Signed-off-by: Andre Przywara --- .../devicetree/bindings/timer/arm,sp804.txt | 29 ------ .../devicetree/bindings/timer/arm,sp804.yaml | 93 +++++++++++++++++++ 2 files changed, 93 insertions(+), 29 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/arm,sp804.txt create mode 100644 Documentation/devicetree/bindings/timer/arm,sp804.yaml diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.txt b/Documentation/devicetree/bindings/timer/arm,sp804.txt deleted file mode 100644 index 5cd8eee74af1..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,sp804.txt +++ /dev/null @@ -1,29 +0,0 @@ -ARM sp804 Dual Timers ---------------------------------------- - -Required properties: -- compatible: Should be "arm,sp804" & "arm,primecell" -- interrupts: Should contain the list of Dual Timer interrupts. This is the - interrupt for timer 1 and timer 2. In the case of a single entry, it is - the combined interrupt or if "arm,sp804-has-irq" is present that - specifies which timer interrupt is connected. -- reg: Should contain location and length for dual timer register. -- clocks: clocks driving the dual timer hardware. This list should be 1 or 3 - clocks. With 3 clocks, the order is timer0 clock, timer1 clock, - apb_pclk. A single clock can also be specified if the same clock is - used for all clock inputs. - -Optional properties: -- arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this - specifies if the irq connection is for timer 1 or timer 2. A value of 1 - or 2 should be used. - -Example: - - timer0: timer@fc800000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xfc800000 0x1000>; - interrupts = <0 0 4>, <0 1 4>; - clocks = <&timclk1 &timclk2 &pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.yaml b/Documentation/devicetree/bindings/timer/arm,sp804.yaml new file mode 100644 index 000000000000..609972379637 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,sp804.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/arm,sp804.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM sp804 Dual Timers + +maintainers: + - Haojian Zhuang + +description: |+ + The Arm SP804 IP implements two independent timers, configurable for + 16 or 32 bit operation and capable of running in one-shot, periodic, or + free-running mode. The input clock is shared, but can be gated and prescaled + independently for each timer. + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,sp804 + required: + - compatible + +properties: + compatible: + items: + - const: arm,sp804 + - const: arm,primecell + + interrupts: + description: | + If two interrupts are listed, those are the interrupts for timer + 1 and 2, respectively. If there is only a single interrupt, it is + either a combined interrupt or the sole interrupt of one timer, as + specified by the "arm,sp804-has-irq" property. + minItems: 1 + maxItems: 2 + + reg: + description: The physical base address of the SP804 IP. + maxItems: 1 + + clocks: + description: | + Clocks driving the dual timer hardware. This list should + be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1 + clock, apb_pclk. A single clock can also be specified if the same + clock is used for all clock inputs. + oneOf: + - items: + - description: clock for timer 1 + - description: clock for timer 2 + - description: bus clock + - items: + - description: unified clock for both timers and the bus + + clock-names: true + # The original binding did not specify any clock names, and there is no + # consistent naming used in the existing DTs. The primecell binding + # requires the "apb_pclk" name, so we need this property. + # Use "timer0clk", "timer1clk", "apb_pclk" for new DTs. + + arm,sp804-has-irq: + description: If only one interrupt line is connected to the interrupt + controller, this property specifies which timer is connected to this + line. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 2 + +required: + - compatible + - interrupts + - reg + - clocks + +additionalProperties: false + +examples: + - | + timer0: timer@fc800000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xfc800000 0x1000>; + interrupts = <0 0 4>, <0 1 4>; + clocks = <&timclk1>, <&timclk2>, <&pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + };