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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=8tun+mNUouTN1gi05pQv0+5fko5re9VKERyIyBMpl10=; b=cjEUc0fPVab1+6altukHN0n0EXvBlpOhkVF+IkBzJDGF9VZwSuOE6hbLweyVvsJ4uK fzoITBJb+vpmdvJOeLWYu2Dnq98hb5AOeTU6evCpXkdlljkFUqF8ZTFOBC1xGPQxKwlx VRTxXsOzDe3orFYa4G7IPJU5PoLZ3LPH6x6cQfkQTfg9+iDDZ2yVduZucJaYddtVa5P3 hxszVgvnsaYV6/ClOQK8JAR0wkiwP7zouF3bKHK6ZPgFMRPiE8KmlG8BGUI+ry0/1rf6 DG2+HFkk1UyreW16LTGbNfr+dl71r5T04y391vJcHNpFcdOkoRYG0iql9OzOpntJv8eV rLQg== X-Gm-Message-State: AOAM532xW+aFMKChGYUxalkUBS0Wtm1TDdVENBByZUtljm+QEIceS7w/ Cshd3fDGevJ1Wvv4kjIOXb6Et/7Vmi8= X-Google-Smtp-Source: ABdhPJx+4w9R7rTpAdHDa+2P8yo/me/0lKUZwjHaFi6O27rkEcpudYYqEBfyZiyTwHgX6y8wNl/xEi8FyvI= X-Received: from ascull.lon.corp.google.com ([2a00:79e0:d:109:4a0f:cfff:fe4a:6363]) (user=ascull job=sendgmr) by 2002:a0c:f48e:: with SMTP id i14mr1950105qvm.5.1599141223418; Thu, 03 Sep 2020 06:53:43 -0700 (PDT) Date: Thu, 3 Sep 2020 14:53:03 +0100 In-Reply-To: <20200903135307.251331-1-ascull@google.com> Message-Id: <20200903135307.251331-15-ascull@google.com> Mime-Version: 1.0 References: <20200903135307.251331-1-ascull@google.com> X-Mailer: git-send-email 2.28.0.402.g5ffc5be6b7-goog Subject: [PATCH v3 14/18] smccc: Cast arguments to unsigned long From: Andrew Scull To: kvmarm@lists.cs.columbia.edu X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200903_095348_040275_74BEB346 X-CRM114-Status: GOOD ( 11.14 ) X-Spam-Score: -8.2 (--------) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-8.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:74a listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -7.5 USER_IN_DEF_DKIM_WL From: address is in the default DKIM white-list 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.5 DKIMWL_WL_MED DKIMwl.org - Medium sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, kernel-team@android.com, suzuki.poulose@arm.com, maz@kernel.org, Sudeep Holla , james.morse@arm.com, Andrew Scull , catalin.marinas@arm.com, will@kernel.org, julien.thierry.kdev@gmail.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org To avoid warning about implicit casting, make the casting explicit. This allows, for example, pointers to be used as arguments as are used in the KVM hyp interface. Cc: Sudeep Holla Signed-off-by: Andrew Scull --- include/linux/arm-smccc.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 15c706fb0a37..3bb109a35554 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -260,7 +260,7 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, typeof(a1) __a1 = a1; \ struct arm_smccc_res *___res = res; \ register unsigned long r0 asm("r0") = (u32)a0; \ - register unsigned long r1 asm("r1") = __a1; \ + register unsigned long r1 asm("r1") = (unsigned long)__a1; \ register unsigned long r2 asm("r2"); \ register unsigned long r3 asm("r3") @@ -269,8 +269,8 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, typeof(a2) __a2 = a2; \ struct arm_smccc_res *___res = res; \ register unsigned long r0 asm("r0") = (u32)a0; \ - register unsigned long r1 asm("r1") = __a1; \ - register unsigned long r2 asm("r2") = __a2; \ + register unsigned long r1 asm("r1") = (unsigned long)__a1; \ + register unsigned long r2 asm("r2") = (unsigned long)__a2; \ register unsigned long r3 asm("r3") #define __declare_arg_3(a0, a1, a2, a3, res) \ @@ -279,29 +279,29 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, typeof(a3) __a3 = a3; \ struct arm_smccc_res *___res = res; \ register unsigned long r0 asm("r0") = (u32)a0; \ - register unsigned long r1 asm("r1") = __a1; \ - register unsigned long r2 asm("r2") = __a2; \ - register unsigned long r3 asm("r3") = __a3 + register unsigned long r1 asm("r1") = (unsigned long)__a1; \ + register unsigned long r2 asm("r2") = (unsigned long)__a2; \ + register unsigned long r3 asm("r3") = (unsigned long)__a3 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ typeof(a4) __a4 = a4; \ __declare_arg_3(a0, a1, a2, a3, res); \ - register unsigned long r4 asm("r4") = __a4 + register unsigned long r4 asm("r4") = (unsigned long)__a4 #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ typeof(a5) __a5 = a5; \ __declare_arg_4(a0, a1, a2, a3, a4, res); \ - register unsigned long r5 asm("r5") = __a5 + register unsigned long r5 asm("r5") = (unsigned long)__a5 #define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ typeof(a6) __a6 = a6; \ __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ - register unsigned long r6 asm("r6") = __a6 + register unsigned long r6 asm("r6") = (unsigned long)__a6 #define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ typeof(a7) __a7 = a7; \ __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ - register unsigned long r7 asm("r7") = __a7 + register unsigned long r7 asm("r7") = (unsigned long)__a7 #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__)