From patchwork Fri Sep 11 08:41:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 11769999 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 53ACB746 for ; Fri, 11 Sep 2020 08:46:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F179920665 for ; Fri, 11 Sep 2020 08:46:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="m+aroZch" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F179920665 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2C8gFdkz6iwMhOrnVWwWmxHw0vdf1KnHQFSHLflXaV0=; b=m+aroZchesigBwfmHGw16YUZ1 bqNgojR4l+bj/LFXhjRKGT4kwnj+Dwp8ky0n2ir/BPSp884UOKRqd/7rAtBOWUW0uK9GtFmv9kyfy Cx64kYn5whJFbOfWNV0qNI7j8EUfAC+YlR9C2aT84YpOQTOnzK4n4e2q2mFLoIZtsJiVlms2CHqsW TOosXOUrda61UWV3liAoMtFuYM9Pd7BCbL1JuM9v5l9txRq/QQrtLvG8oxz5B3tJyWEuZPQMWxpf1 4klebk+Z/UD8+3xzJ0zR6x4h74omVe+rvDRzDSRpeq7hCiEgE5bYAxJlpvOzIuMpa0R29g0WRw/aA BJe2YX2tw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kGefG-0002OZ-R5; Fri, 11 Sep 2020 08:44:14 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kGecs-0001Ig-Rt for linux-arm-kernel@lists.infradead.org; Fri, 11 Sep 2020 08:41:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6D5BC15EC; Fri, 11 Sep 2020 01:41:46 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6E46B3F73C; Fri, 11 Sep 2020 01:41:45 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 15/19] coresight: etm4x: Use TRCDEVARCH for component discovery Date: Fri, 11 Sep 2020 09:41:15 +0100 Message-Id: <20200911084119.1080694-16-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200911084119.1080694-1-suzuki.poulose@arm.com> References: <20200911084119.1080694-1-suzuki.poulose@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200911_044147_027532_F6E98AA9 X-CRM114-Status: GOOD ( 17.61 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mathieu.poirier@linaro.org, Suzuki K Poulose , coresight@lists.linaro.org, Anshuman.Khandual@arm.com, leo.yan@linaro.org, mike.leach@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org We have been using TRCIDR1 for detecting the ETM version. As we are about to discover the trace unit on a CPU, let us use a CoreSight architected register, instead of an ETM architected register for accurate detection on a CPU. e.g, a CPU might implement a custom trace unit, not an ETM. Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etm4x.c | 50 ++++++++++--------- drivers/hwtracing/coresight/coresight-etm4x.h | 4 +- 2 files changed, 29 insertions(+), 25 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 5880f105268f..0fce9fb12cff 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -61,6 +61,17 @@ struct etm_init_arg { struct csdev_access *csa; }; +static inline u8 etm_devarch_arch(u32 devarch) +{ + return (devarch >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & 0xfUL; +} + +static inline u8 etm_devarch_rev(u32 devarch) +{ + return (devarch & ETM_DEVARCH_REVISION_MASK) >> + ETM_DEVARCH_REVISION_SHIFT; +} + u64 etm4x_sysreg_read(struct csdev_access *csa, u32 offset, bool _relaxed, @@ -149,18 +160,6 @@ static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, CS_UNLOCK(csa); } -static bool etm4_arch_supported(u8 arch) -{ - /* Mask out the minor version number */ - switch (arch & 0xf0) { - case ETM_ARCH_V4: - break; - default: - return false; - } - return true; -} - static int etm4_cpu_id(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -694,10 +693,23 @@ static void etm_detect_lock_status(struct etmv4_drvdata *drvdata, drvdata->os_lock_model = TRCOSLSR_OSM(os_lsr); } +static inline bool trace_unit_supported(u32 devarch) +{ + return (devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH; +} + static bool etm_init_iomem_access(struct etmv4_drvdata *drvdata, struct csdev_access *csa) { + u32 devarch; + + devarch = readl_relaxed(drvdata->base + TRCDEVARCH); + if (!trace_unit_supported(devarch)) + return false; + *csa = CSDEV_ACCESS_IOMEM(drvdata->base); + drvdata->arch = devarch; + return true; } @@ -713,7 +725,6 @@ static bool etm_init_csdev_access(struct etmv4_drvdata *drvdata, static void etm4_init_arch_data(void *info) { u32 etmidr0; - u32 etmidr1; u32 etmidr2; u32 etmidr3; u32 etmidr4; @@ -784,14 +795,6 @@ static void etm4_init_arch_data(void *info) /* TSSIZE, bits[28:24] Global timestamp size field */ drvdata->ts_size = BMVAL(etmidr0, 24, 28); - /* base architecture of trace unit */ - etmidr1 = etm4x_relaxed_read32(csa, TRCIDR1); - /* - * TRCARCHMIN, bits[7:4] architecture the minor version number - * TRCARCHMAJ, bits[11:8] architecture major versin number - */ - drvdata->arch = BMVAL(etmidr1, 4, 11); - /* maximum size of resources */ etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); /* CIDSIZE, bits[9:5] Indicates the Context ID size */ @@ -1618,7 +1621,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) etm4_init_arch_data, &init_arg, 1)) dev_err(dev, "ETM arch init failed\n"); - if (etm4_arch_supported(drvdata->arch) == false) { + if (!drvdata->arch) { ret = -EINVAL; goto err_arch_supported; } @@ -1653,7 +1656,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n", - drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf); + drvdata->cpu, etm_devarch_arch(drvdata->arch), + etm_devarch_rev(drvdata->arch)); if (boot_enable) { coresight_enable(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 277c22540db6..b217f16ad921 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -730,7 +730,7 @@ struct etmv4_save_state { * @spinlock: Only one at a time pls. * @mode: This tracer's mode, i.e sysFS, Perf or disabled. * @cpu: The cpu this component is affined to. - * @arch: ETM version number. + * @arch: ETM device architecture register. * @nr_pe: The number of processing entity available for tracing. * @nr_pe_cmp: The number of processing entity comparator inputs that are * available for tracing. @@ -793,7 +793,7 @@ struct etmv4_drvdata { spinlock_t spinlock; local_t mode; int cpu; - u8 arch; + u32 arch; u8 nr_pe; u8 nr_pe_cmp; u8 nr_addr_cmp;