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[1/1] dt-bindings: sp804: add support for Hisilicon sp804 timer

Message ID 20200919124412.4135-2-thunder.leizhen@huawei.com (mailing list archive)
State New, archived
Headers show
Series clocksource: sp804: add support for Hisilicon sp804 timer | expand

Commit Message

Leizhen (ThunderTown) Sept. 19, 2020, 12:44 p.m. UTC
Some Hisilicon SoCs, such as Hi1212, use the Hisilicon extended sp804
timer.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 Documentation/devicetree/bindings/timer/arm,sp804.yaml | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

Comments

Rob Herring (Arm) Sept. 23, 2020, 9 p.m. UTC | #1
On Sat, 19 Sep 2020 20:44:12 +0800, Zhen Lei wrote:
> Some Hisilicon SoCs, such as Hi1212, use the Hisilicon extended sp804
> timer.
> 
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> ---
>  Documentation/devicetree/bindings/timer/arm,sp804.yaml | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 

Applied, thanks!
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.yaml b/Documentation/devicetree/bindings/timer/arm,sp804.yaml
index ba0945cf799ee0b..e35d3053250a557 100644
--- a/Documentation/devicetree/bindings/timer/arm,sp804.yaml
+++ b/Documentation/devicetree/bindings/timer/arm,sp804.yaml
@@ -15,19 +15,26 @@  description: |+
   free-running mode. The input clock is shared, but can be gated and prescaled
   independently for each timer.
 
+  There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
+  SoCs, such as Hi1212, should use the dedicated compatible: "hisilicon,sp804".
+
 # Need a custom select here or 'arm,primecell' will match on lots of nodes
 select:
   properties:
     compatible:
       contains:
-        const: arm,sp804
+        oneOf:
+          - const: arm,sp804
+          - const: hisilicon,sp804
   required:
     - compatible
 
 properties:
   compatible:
     items:
-      - const: arm,sp804
+      - enum:
+        - arm,sp804
+        - hisilicon,sp804
       - const: arm,primecell
 
   interrupts: