From patchwork Tue Sep 22 10:12:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11792065 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A8A506CB for ; Tue, 22 Sep 2020 10:14:50 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5A520238D6 for ; Tue, 22 Sep 2020 10:14:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Ot+Q1L56" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5A520238D6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/FTVdGO8vnQeFtFIejK+JPFBKXyj4aLROrqUJk7GkGU=; b=Ot+Q1L56YYV3vavje/TFsMimAh 4LT6CI0PAzHbCIsnyYDVkFZLJekGuHVdkaesaEgwPr4dUMPX2B4PGU8zVC30DEm8QKbfwsQVvFEa2 DpAil5ThOGciicujzc7S1UbKb++Nr2T8EGIZbQpuNt1dUVz9iACJp7y8RU7X7HV/i8wBtweEAq1GC plcLPaDWiQQ1JrGw05oWOoXCX0a8JEfF/CYaBQrkcqj8IUsDvGUXubcv45tb4oSZARHpRne/GENeC 6/hlA0duNTBmbd81xm63U2KC/5jZsm2xCOXHHPNe/vUX4JWS1Uu6W4qTZftv6JAzkvVwA99GjdKFW x58T2dmw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKfI8-0006YM-SR; Tue, 22 Sep 2020 10:12:56 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKfHs-0006T9-JL for linux-arm-kernel@lists.infradead.org; Tue, 22 Sep 2020 10:12:44 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2168512FC; Tue, 22 Sep 2020 03:12:34 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.195.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 242653F718; Tue, 22 Sep 2020 03:12:32 -0700 (PDT) From: Andre Przywara To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo Subject: [PATCH 1/5] arm64: spe: Allow new bits in SPE filter register Date: Tue, 22 Sep 2020 11:12:21 +0100 Message-Id: <20200922101225.183554-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200922101225.183554-1-andre.przywara@arm.com> References: <20200922101225.183554-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200922_061241_040282_9C89D505 X-CRM114-Status: GOOD ( 13.61 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Suzuki K Poulose , Alexander Shishkin , linux-kernel@vger.kernel.org, James Clark , Leo Yan , Namhyung Kim , Jiri Olsa , Tan Xiaojun , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The ARMv8.3-SPE extension adds some new bits for the event filter. Remove bits 11, 17 and 18 from the RES0 mask, so they can be used correctly. Signed-off-by: Andre Przywara --- arch/arm64/include/asm/sysreg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 554a7e8ecb07..efca4ee28671 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -281,7 +281,7 @@ #define SYS_PMSFCR_EL1_ST_SHIFT 18 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) -#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL +#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00f90755UL #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0