From patchwork Wed Sep 30 15:50:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 11809761 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDEA6618 for ; Wed, 30 Sep 2020 15:52:56 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A95F20789 for ; Wed, 30 Sep 2020 15:52:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Ad6QCQ0R" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9A95F20789 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Subject:MIME-Version:References:In-Reply-To: Message-Id:Date:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=vGSW6TN86s3+7Ko5NMVqIgjGkDnqzfF7njzI1AOcks4=; b=Ad6QCQ0RxAF6dFK28ATmXbNgZ zS/jKtsJAoX32403nBc40nPk39ZOUa0FibfU3nGJklq0+8HjfbohaUFx1HCQDKGtDoNI+aqBcWH7v Y8ICW8pMXM9YAVmLrFMN9az1iG5jmTodwi7Nc1PVJc7LS8MB8S6GfTXCtBCffMl1d78miRAlAXUk3 fBmfkVoEiUTFC8Aueanjj0eyAixXJZDlG1Q9fVVTt2QnwxLZm/EisgeqhrxKmIOYQIdN55IwCKU73 iAtIGV4V0II3R6wmFrLSSxKdbsnp9e15e4LCAs82l8qF8fy54rnFdAYHVhmGBq2F0fcnBzphVZcco CpKSMz/mQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kNeNh-0001d1-8L; Wed, 30 Sep 2020 15:51:01 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kNeN2-0001SJ-Is for linux-arm-kernel@lists.infradead.org; Wed, 30 Sep 2020 15:50:22 +0000 Received: from [2a0a:edc0:0:1101:1d::39] (helo=dude03.red.stw.pengutronix.de) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1kNeMx-0006WU-R1; Wed, 30 Sep 2020 17:50:16 +0200 From: Lucas Stach To: Shawn Guo , Rob Herring Date: Wed, 30 Sep 2020 17:50:02 +0200 Message-Id: <20200930155006.535712-8-l.stach@pengutronix.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200930155006.535712-1-l.stach@pengutronix.de> References: <20200930155006.535712-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-1.5 required=4.0 tests=AWL,BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_SOFTFAIL,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Subject: [PATCH 07/11] soc: imx: gpcv2: add support for optional resets X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200930_115020_680784_A68CC2B4 X-CRM114-Status: GOOD ( 17.79 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , devicetree@vger.kernel.org, Frieder Schrempf , patchwork-lst@pengutronix.de, NXP Linux Team , kernel@pengutronix.de, Fabio Estevam , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Normally the reset for the devices inside the power domain is triggered automatically from the PGC in the power-up sequencing, however on i.MX8MM this doesn't work for the GPU power domains. Add support for triggering the reset explicitly during the power up sequencing. Signed-off-by: Lucas Stach --- .../devicetree/bindings/power/fsl,imx-gpcv2.yaml | 6 ++++++ drivers/soc/imx/gpcv2.c | 13 +++++++++++++ 2 files changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index bde09a0b2da3..9773771b9000 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -62,6 +62,12 @@ properties: power-supply: true + resets: + description: | + A number of phandles to resets that need to be asserted during + power-up sequencing of the domain. + minItems: 1 + required: - '#power-domain-cells' - reg diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index db93fef0c76b..76aa8a67d8a7 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -112,6 +113,7 @@ struct imx_pgc_domain { struct regulator *regulator; struct clk *clk[GPC_CLK_MAX]; int num_clks; + struct reset_control *reset; unsigned int pgc; @@ -167,6 +169,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) } } + reset_control_assert(domain->reset); + if (domain->bits.pxx) { /* request the domain to power up */ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, @@ -189,6 +193,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) GPC_PGC_CTRL_PCR, 0); } + reset_control_deassert(domain->reset); + /* request the ADB400 to power up */ if (domain->bits.hskreq) { regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, @@ -577,6 +583,13 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) domain->voltage, domain->voltage); } + domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev); + if (IS_ERR(domain->reset)) { + if (PTR_ERR(domain->reset) != -EPROBE_DEFER) + dev_err(domain->dev, "Failed to get domain's reset\n"); + return PTR_ERR(domain->reset); + } + ret = imx_pgc_get_clocks(domain); if (ret) { if (ret != -EPROBE_DEFER)