| Message ID | 20201005133256.1390543-1-maz@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: tegra: Fix GIC400 missing GICH/GICV register regions | expand |
On Mon, Oct 05, 2020 at 02:32:56PM +0100, Marc Zyngier wrote: > GIC400 has full support for virtualization, and yet the tegra186 > DT doesn't expose the GICH/GICV regions (despite exposing the > maintenance interrupt that only makes sense for virtualization). > > Add the missing regions, based on the hunch that the HW doesn't > use the CPU build-in interfaces, but instead the external ones > provided by the GIC. KVM's virtual GIC now works with this change. > > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Applied, thanks. Thierry
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 8eb61dd9921e..fd44545e124d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -630,7 +630,9 @@ gic: interrupt-controller@3881000 { #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x03881000 0x0 0x1000>, - <0x0 0x03882000 0x0 0x2000>; + <0x0 0x03882000 0x0 0x2000>, + <0x0 0x03884000 0x0 0x2000>, + <0x0 0x03886000 0x0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupt-parent = <&gic>;
GIC400 has full support for virtualization, and yet the tegra186 DT doesn't expose the GICH/GICV regions (despite exposing the maintenance interrupt that only makes sense for virtualization). Add the missing regions, based on the hunch that the HW doesn't use the CPU build-in interfaces, but instead the external ones provided by the GIC. KVM's virtual GIC now works with this change. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)