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Mon, 5 Oct 2020 15:43:09 +0200 (CEST) From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/3] drm/exynos: Scale the DSIM PHY HFP/HBP/HSA to lanes and bpp Date: Mon, 5 Oct 2020 15:42:49 +0200 Message-Id: <20201005134250.527153-2-marex@denx.de> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201005134250.527153-1-marex@denx.de> References: <20201005134250.527153-1-marex@denx.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201005_094314_529256_D6580A0F X-CRM114-Status: GOOD ( 13.51 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [212.18.0.9 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [212.18.0.9 listed in wl.mailspike.net] 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , linux-samsung-soc@vger.kernel.org, Shawn Guo , =?utf-8?q?Guido_G=C3=BCnther?= , Michael Tretter , Jaehoon Chung , NXP Linux Team , Lucas Stach , Fabio Estevam , linux-arm-kernel@lists.infradead.org, Marek Szyprowski Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The value programmed into horizontal porch and sync registers must be scaled to the correct number of DSI lanes and bpp, make it so. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Guido Günther Cc: Jaehoon Chung Cc: Lucas Stach Cc: Marek Szyprowski Cc: Michael Tretter Cc: NXP Linux Team Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org To: dri-devel@lists.freedesktop.org --- NOTE: This depends on https://patchwork.kernel.org/project/dri-devel/list/?series=347439 --- drivers/gpu/drm/bridge/samsung-dsim.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index fbd87a74eb9f..42b49546dd00 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -740,20 +740,23 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) { struct drm_display_mode *m = &dsi->mode; unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; + int bpp; u32 reg; if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { + bpp = mipi_dsi_pixel_format_to_bpp(dsi->format) / 8; + reg = DSIM_CMD_ALLOW(0xf) | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); - reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) - | DSIM_MAIN_HBP(m->htotal - m->hsync_end); + reg = DSIM_MAIN_HFP((m->hsync_start - m->hdisplay) * bpp / dsi->lanes) + | DSIM_MAIN_HBP((m->htotal - m->hsync_end) * bpp / dsi->lanes); samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) - | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); + | DSIM_MAIN_HSA((m->hsync_end - m->hsync_start) * bpp / dsi->lanes); samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); } reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |