Message ID | 20201006200316.2261245-4-lars.povlsen@microchip.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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IronPort-SDR: HimIamFIHSYsKJWcbtGx7BoicFyTCArkf7FWTVPPuEgklbdtF6u+PMCgy2ODy3//eyMxYLeVGg q6k/fg70k4Co/DeLbJjKqboiQ7nLZIXxX53nGlsmwckgJqhnlVLgouLKTlQZ09k5cvklz1EfPU aaauVcXITegDQUR0Q0pb4iY440wqYmw7KAXf3ci0a+33UK33lknI2euLNrvfjSKpVv0gGDtWSW ZCVaiWNF/pM53W1/Fw2om+NsDQ19hw/YtfK4yD837YCLP1WYZQdWMceuFCLhkh50C+UUrvy+6k xcM= X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="93635019" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Oct 2020 13:03:57 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Tue, 6 Oct 2020 13:03:56 -0700 Received: from soft-dev10.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Tue, 6 Oct 2020 13:03:54 -0700 From: Lars Povlsen <lars.povlsen@microchip.com> To: Sebastian Reichel <sre@kernel.org> Subject: [PATCH v2 3/3] arm64: dts: sparx5: Add reset support Date: Tue, 6 Oct 2020 22:03:16 +0200 Message-ID: <20201006200316.2261245-4-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201006200316.2261245-1-lars.povlsen@microchip.com> References: <20201006200316.2261245-1-lars.povlsen@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_160359_201120_09E5D7B0 X-CRM114-Status: GOOD ( 10.45 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.150.166 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [216.71.150.166 listed in wl.mailspike.net] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <linux-arm-kernel.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-arm-kernel>, <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/> List-Post: <mailto:linux-arm-kernel@lists.infradead.org> List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>, <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe> Cc: devicetree@vger.kernel.org, Alexandre Belloni <alexandre.belloni@bootlin.com>, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>, linux-arm-kernel@lists.infradead.org, Lars Povlsen <lars.povlsen@microchip.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org |
Series |
power: Add reset support for Microchip Sparx5 SoC
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expand
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diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index a84ffd3069d4..016be6d27a6b 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -118,6 +118,16 @@ gic: interrupt-controller@600300000 { interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + cpu_ctrl: syscon@600000000 { + compatible = "microchip,sparx5-cpu-syscon", "syscon"; + reg = <0x6 0x00000000 0xd0>; + }; + + reset@611010008 { + compatible = "microchip,sparx5-chip-reset"; + reg = <0x6 0x11010008 0x4>; + }; + uart0: serial@600100000 { pinctrl-0 = <&uart_pins>; pinctrl-names = "default";
This adds reset support to the Sparx5 SoC DT. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.25.1