diff mbox series

arm64: dts: imx8mm-beacon-som: Add QSPI NOR flash support

Message ID 20201007142409.235234-1-aford173@gmail.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: imx8mm-beacon-som: Add QSPI NOR flash support | expand

Commit Message

Adam Ford Oct. 7, 2020, 2:24 p.m. UTC 
imx8mm-beacon-som has a Quad-SPI NOR flash connected to the FlexSPI bus.

This patch enables the FlexSPI bus and configures it to work with the
flash part.

Signed-off-by: Adam Ford <aford173@gmail.com>

Comments

Shawn Guo Oct. 30, 2020, 8:01 a.m. UTC | #1 
On Wed, Oct 07, 2020 at 09:24:08AM -0500, Adam Ford wrote:
> imx8mm-beacon-som has a Quad-SPI NOR flash connected to the FlexSPI bus.
> 
> This patch enables the FlexSPI bus and configures it to work with the
> flash part.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>

Applied, thanks.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
index 397cf8b2f29b..b65059f715cd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
@@ -75,6 +75,22 @@  ethphy0: ethernet-phy@0 {
 	};
 };
 
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi>;
+	status = "okay";
+
+	flash@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <80000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
@@ -304,6 +320,17 @@  MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
 			>;
 		};
 
+		pinctrl_flexspi: flexspigrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
+				MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
+				MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
+				MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
+				MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
+				MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
+			>;
+		};
+
 		pinctrl_pmic: pmicirqgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141