diff mbox series

ARM: at91: sam9x60 SiP types added to soc description

Message ID 20201008125028.21071-1-nicolas.ferre@microchip.com (mailing list archive)
State New, archived
Headers show
Series ARM: at91: sam9x60 SiP types added to soc description | expand

Commit Message

Nicolas Ferre Oct. 8, 2020, 12:50 p.m. UTC 
From: Kai Stuhlemmer <kai.stuhlemmer@ebee.de>

Adding SAM9X60 SIP variants to the soc description list.

Signed-off-by: Kai Stuhlemmer <kai.stuhlemmer@ebee.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
 drivers/soc/atmel/soc.c | 6 ++++++
 drivers/soc/atmel/soc.h | 3 +++
 2 files changed, 9 insertions(+)

Comments

Alexandre Belloni Oct. 28, 2020, 8:28 p.m. UTC | #1 
On Thu, 8 Oct 2020 14:50:28 +0200, nicolas.ferre@microchip.com wrote:
> Adding SAM9X60 SIP variants to the soc description list.

Applied, thanks!

[1/1] ARM: at91: sam9x60 SiP types added to soc description
      commit: 786c395dbe4216c2349914952b8cdb57ea8a326a

Best regards,
diff mbox series

Patch

diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
index 55a1f57a4d8c..c4472b68b7c2 100644
--- a/drivers/soc/atmel/soc.c
+++ b/drivers/soc/atmel/soc.c
@@ -69,6 +69,12 @@  static const struct at91_soc __initconst socs[] = {
 #endif
 #ifdef CONFIG_SOC_SAM9X60
 	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"),
+	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH,
+		 "sam9x60 64MiB DDR2 SiP", "sam9x60"),
+	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH,
+		 "sam9x60 128MiB DDR2 SiP", "sam9x60"),
+	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH,
+		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
 #endif
 #ifdef CONFIG_SOC_SAMA5
 	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
index ee652e4841a5..5849846a69d6 100644
--- a/drivers/soc/atmel/soc.h
+++ b/drivers/soc/atmel/soc.h
@@ -60,6 +60,9 @@  at91_soc_init(const struct at91_soc *socs);
 #define AT91SAM9CN11_EXID_MATCH		0x00000009
 
 #define SAM9X60_EXID_MATCH		0x00000000
+#define SAM9X60_D5M_EXID_MATCH		0x00000001
+#define SAM9X60_D1G_EXID_MATCH		0x00000010
+#define SAM9X60_D6K_EXID_MATCH		0x00000011
 
 #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
 #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0