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Received: from twspam01.aspeedtech.com ([211.20.114.71]) by casper.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kRoZn-0003vq-Ow for linux-arm-kernel@lists.infradead.org; Mon, 12 Oct 2020 03:33:14 +0000 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 09C3Tp4U087377; Mon, 12 Oct 2020 11:29:51 +0800 (GMT-8) (envelope-from billy_tsai@aspeedtech.com) Received: from localhost.localdomain (192.168.10.9) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Oct 2020 11:32:01 +0800 From: Billy Tsai To: , , , , , , , , , , Subject: [PATCH 3/3] pinctrl: aspeed-g6: Add sgpiom2 pinctrl setting Date: Mon, 12 Oct 2020 11:31:50 +0800 Message-ID: <20201012033150.21056-4-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201012033150.21056-1-billy_tsai@aspeedtech.com> References: <20201012033150.21056-1-billy_tsai@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.9] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 09C3Tp4U087377 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201012_043246_882220_E3AC8E3B X-CRM114-Status: GOOD ( 11.72 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.4 on casper.infradead.org summary: Content analysis details: (-1.9 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 SPF_FAIL SPF: sender does not match SPF record (fail) [SPF failed: Please see http://www.openspf.org/Why?s=mfrom; id=billy_tsai%40aspeedtech.com; ip=211.20.114.71; r=casper.infradead.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org At ast2600a1 we change feature of master sgpio to 2 sets. So this patch is used to add the pinctrl setting of the new sgpio. Signed-off-by: Billy Tsai Reviewed-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 5 ++++ drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 30 +++++++++++++++++++--- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 7028e21bdd98..a16ecf08e307 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -862,6 +862,11 @@ groups = "SGPM1"; }; + pinctrl_sgpm2_default: sgpm2_default { + function = "SGPM2"; + groups = "SGPM2"; + }; + pinctrl_sgps1_default: sgps1_default { function = "SGPS1"; groups = "SGPS1"; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 34803a6c7664..b673a44ffa3b 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -46,8 +46,10 @@ #define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */ #define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */ #define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */ +#define SCU690 0x690 /* Multi-function Pin Control #24 */ #define SCU694 0x694 /* Multi-function Pin Control #25 */ #define SCU69C 0x69C /* Multi-function Pin Control #27 */ +#define SCU6D0 0x6D0 /* Multi-function Pin Control #28 */ #define SCUC20 0xC20 /* PCIE configuration Setting Control */ #define ASPEED_G6_NR_PINS 256 @@ -81,13 +83,21 @@ FUNC_GROUP_DECL(I2C12, L26, K24); #define K26 4 SIG_EXPR_LIST_DECL_SESG(K26, MACLINK1, MACLINK1, SIG_DESC_SET(SCU410, 4)); SIG_EXPR_LIST_DECL_SESG(K26, SCL13, I2C13, SIG_DESC_SET(SCU4B0, 4)); -PIN_DECL_2(K26, GPIOA4, MACLINK1, SCL13); +/*SGPM2 is A1 Only */ +SIG_EXPR_LIST_DECL_SESG(K26, SGPM2CLK, SGPM2, SIG_DESC_SET(SCU6D0, 4), + SIG_DESC_CLEAR(SCU410, 4), SIG_DESC_CLEAR(SCU4B0, 4), + SIG_DESC_CLEAR(SCU690, 4)); +PIN_DECL_3(K26, GPIOA4, SGPM2CLK, MACLINK1, SCL13); FUNC_GROUP_DECL(MACLINK1, K26); #define L24 5 SIG_EXPR_LIST_DECL_SESG(L24, MACLINK2, MACLINK2, SIG_DESC_SET(SCU410, 5)); SIG_EXPR_LIST_DECL_SESG(L24, SDA13, I2C13, SIG_DESC_SET(SCU4B0, 5)); -PIN_DECL_2(L24, GPIOA5, MACLINK2, SDA13); +/*SGPM2 is A1 Only */ +SIG_EXPR_LIST_DECL_SESG(L24, SGPM2LD, SGPM2, SIG_DESC_SET(SCU6D0, 5), + SIG_DESC_CLEAR(SCU410, 5), SIG_DESC_CLEAR(SCU4B0, 5), + SIG_DESC_CLEAR(SCU690, 5)); +PIN_DECL_3(L24, GPIOA5, SGPM2LD, MACLINK2, SDA13); FUNC_GROUP_DECL(MACLINK2, L24); FUNC_GROUP_DECL(I2C13, K26, L24); @@ -95,16 +105,26 @@ FUNC_GROUP_DECL(I2C13, K26, L24); #define L23 6 SIG_EXPR_LIST_DECL_SESG(L23, MACLINK3, MACLINK3, SIG_DESC_SET(SCU410, 6)); SIG_EXPR_LIST_DECL_SESG(L23, SCL14, I2C14, SIG_DESC_SET(SCU4B0, 6)); -PIN_DECL_2(L23, GPIOA6, MACLINK3, SCL14); +/*SGPM2 is A1 Only */ +SIG_EXPR_LIST_DECL_SESG(L23, SGPM2O, SGPM2, SIG_DESC_SET(SCU6D0, 6), + SIG_DESC_CLEAR(SCU410, 6), SIG_DESC_CLEAR(SCU4B0, 6), + SIG_DESC_CLEAR(SCU690, 6)); +PIN_DECL_3(L23, GPIOA6, SGPM2O, MACLINK3, SCL14); FUNC_GROUP_DECL(MACLINK3, L23); #define K25 7 SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7)); SIG_EXPR_LIST_DECL_SESG(K25, SDA14, I2C14, SIG_DESC_SET(SCU4B0, 7)); -PIN_DECL_2(K25, GPIOA7, MACLINK4, SDA14); +/*SGPM2 is A1 Only */ +SIG_EXPR_LIST_DECL_SESG(K25, SGPM2I, SGPM2, SIG_DESC_SET(SCU6D0, 7), + SIG_DESC_CLEAR(SCU410, 7), SIG_DESC_CLEAR(SCU4B0, 7), + SIG_DESC_CLEAR(SCU690, 7)); +PIN_DECL_3(K25, GPIOA7, SGPM2I, MACLINK4, SDA14); FUNC_GROUP_DECL(MACLINK4, K25); FUNC_GROUP_DECL(I2C14, L23, K25); +/*SGPM2 is A1 Only */ +FUNC_GROUP_DECL(SGPM2, K26, L24, L23, K25); #define J26 8 SIG_EXPR_LIST_DECL_SESG(J26, SALT1, SALT1, SIG_DESC_SET(SCU410, 8)); @@ -2060,6 +2080,7 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { ASPEED_PINCTRL_GROUP(EMMCG4), ASPEED_PINCTRL_GROUP(EMMCG8), ASPEED_PINCTRL_GROUP(SGPM1), + ASPEED_PINCTRL_GROUP(SGPM2), ASPEED_PINCTRL_GROUP(SGPS1), ASPEED_PINCTRL_GROUP(SIOONCTRL), ASPEED_PINCTRL_GROUP(SIOPBI), @@ -2276,6 +2297,7 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(SD1), ASPEED_PINCTRL_FUNC(SD2), ASPEED_PINCTRL_FUNC(SGPM1), + ASPEED_PINCTRL_FUNC(SGPM2), ASPEED_PINCTRL_FUNC(SGPS1), ASPEED_PINCTRL_FUNC(SIOONCTRL), ASPEED_PINCTRL_FUNC(SIOPBI),