From patchwork Tue Oct 13 12:50:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 11835849 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C22CDA732 for ; Tue, 13 Oct 2020 18:11:51 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F01F82256D for ; Tue, 13 Oct 2020 12:51:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ACHcqJXg" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F01F82256D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=lM7HY7tJkzLwFH7QR5cVX3TMNcHGudq7pQy0UY808UI=; b=ACHcqJXge5T2tszzGs3ZT7vzG XV0h/+Q+TT3DasObpBfXfeamUyvJTrTLP174EjmiOd50XOSoskQ50tBfFnOR26W40Mg6DVPw1eALT x4mq79tNklAJHupJUZFhyeefPccpzgsPVwkpeHsJjZIDKtoP78P0no8/R6QrVp/crwwnUBbh5DGKT x1Ym+PjgucM0cxYS1Fx80ICbQFAObe75CA1ES3NpVtvK5ojqS9Gz9VPNvg9YDpJPt2zyvkNxFSW0R QKs/js/lJwCJCk0S0+4qkBrYs9zonLQwqdGguAIuz5bjiOLBiIYAmB4oW6y2kdBVV5E1crzFTrFcN F2ixbzrBQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kSJli-00082j-OT; Tue, 13 Oct 2020 12:51:07 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kSJlg-00081m-FY for linux-arm-kernel@lists.infradead.org; Tue, 13 Oct 2020 12:51:05 +0000 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kSJlE-0007le-2A; Tue, 13 Oct 2020 14:50:36 +0200 Received: from sha by dude.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1kSJlC-0005qL-Lp; Tue, 13 Oct 2020 14:50:34 +0200 From: Sascha Hauer To: linux-edac@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: edac: Add binding for L1/L2 error detection for Cortex A53/57 Date: Tue, 13 Oct 2020 14:50:31 +0200 Message-Id: <20201013125033.4749-2-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201013125033.4749-1-s.hauer@pengutronix.de> References: <20201013125033.4749-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201013_085104_536162_8B50F9A7 X-CRM114-Status: GOOD ( 18.58 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Tony Luck , Sascha Hauer , Rob Herring , Robert Richter , James Morse , kernel@pengutronix.de, Borislav Petkov , York Sun , Mauro Carvalho Chehab , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The ARM Cortex-A53 and A57 CPUs support error detection for the L1/L2 caches. This patch adds a binding for the corresponding driver. Signed-off-by: Sascha Hauer --- .../bindings/edac/arm,cortex-a5x-edac.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml diff --git a/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml b/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml new file mode 100644 index 000000000000..de9325b688a0 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/arm,cortex-a5x-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM cortex A53/A57 EDAC bindings + +description: |+ + This contains the binding to support error detection for the L1 and L2 caches + on ARM Cortex A53 and A57 cores. + +properties: + compatible: + items: + - const: arm,cortex-a53-edac + - const: arm,cortex-a57-edac + + cpus: + minItems: 1 + description: phandles to the cpu nodes this device handles + +required: + - compatible + - cpus + +examples: + - | + edac-a53 { + compatible = "arm,cortex-a53-edac"; + cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; + };