From patchwork Tue Oct 27 17:26:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Elisei X-Patchwork-Id: 11861161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D5CAC388F9 for ; Tue, 27 Oct 2020 17:27:15 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3240C21D24 for ; Tue, 27 Oct 2020 17:27:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="OSYn3tXM" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3240C21D24 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TMoqV9vMKIhe7dlbQibQ3bDYAgT3h7Ggq5Hzn7JDCO8=; b=OSYn3tXM1KKbCIhUZljop5SHh EvXxDJo9T4yQJPDAeJWJnLcg9AKersxopvNxZBlNvjRykEYN1S384SNfS6+CLolUUo3oiWGyxY9CD vMO4n80twksskW7lMwRZvGkbVTVqx67V5cAdlQpU+pSfZNxjxZls6S7n/7tf/uZjoxUVrzy72Ot/m N2/UkQ1EBMT3AqSPTyq0yk+sfaw16/NIBNeJNgGe7/lJ7pYcVcNcQ4Koz5vZUEwdQQGt4jWl09jqG iIqj6Ooi72PDpT/pSMAMBGPWQ95goXC9d3NMV9EKUDYPzZE0DxUzTYXvQYY1f5FrbdtADLcL3AaPj 2TYP2tAZA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXSk5-0004uw-Px; Tue, 27 Oct 2020 17:26:42 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXSjk-0004nw-Cf for linux-arm-kernel@lists.infradead.org; Tue, 27 Oct 2020 17:26:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D469E15AB; Tue, 27 Oct 2020 10:26:19 -0700 (PDT) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CD1BE3F719; Tue, 27 Oct 2020 10:26:18 -0700 (PDT) From: Alexandru Elisei To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Subject: [RFC PATCH v3 04/16] arm64: Introduce CPU SPE feature Date: Tue, 27 Oct 2020 17:26:53 +0000 Message-Id: <20201027172705.15181-5-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.29.1 In-Reply-To: <20201027172705.15181-1-alexandru.elisei@arm.com> References: <20201027172705.15181-1-alexandru.elisei@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_132620_579010_D6EC183B X-CRM114-Status: GOOD ( 17.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: maz@kernel.org, will@kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Detect Statistical Profiling Extension (SPE) support using the cpufeatures framework. The presence of SPE is reported via the ARM64_SPE capability. The feature will be necessary for emulating SPE in KVM, because KVM needs that all CPUs have SPE hardware to avoid scheduling a VCPU on a CPU without support. For this reason, the feature type ARM64_CPUCAP_SYSTEM_FEATURE has been selected to disallow hotplugging a CPU which doesn't support SPE. Signed-off-by: Alexandru Elisei --- arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpufeature.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 42868dbd29fd..10fd094d9a5b 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -65,7 +65,8 @@ #define ARM64_HAS_ARMv8_4_TTL 55 #define ARM64_HAS_TLB_RANGE 56 #define ARM64_MTE 57 +#define ARM64_SPE 58 -#define ARM64_NCAPS 58 +#define ARM64_NCAPS 59 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index dcc165b3fc04..4a0f4dc53824 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1278,6 +1278,18 @@ has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) return has_cpuid_feature(entry, scope); } +static bool __maybe_unused +has_usable_spe(const struct arm64_cpu_capabilities *entry, int scope) +{ + u64 pmbidr; + + if (!has_cpuid_feature(entry, scope)) + return false; + + pmbidr = read_sysreg_s(SYS_PMBIDR_EL1); + return !(pmbidr & BIT(SYS_PMBIDR_EL1_P_SHIFT)); +} + /* * This check is triggered during the early boot before the cpufeature * is initialised. Checking the status on the local CPU allows the boot @@ -2003,6 +2015,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .min_field_value = 1, .cpu_enable = cpu_enable_cnp, }, +#endif +#ifdef CONFIG_ARM_SPE_PMU + { + .desc = "Statistical Profiling Extension (SPE)", + .capability = ARM64_SPE, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .matches = has_usable_spe, + .sys_reg = SYS_ID_AA64DFR0_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64DFR0_PMSVER_SHIFT, + .min_field_value = 1, + }, #endif { .desc = "Speculation barrier (SB)",