From patchwork Tue Oct 27 17:26:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Elisei X-Patchwork-Id: 11861159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81C01C4363A for ; Tue, 27 Oct 2020 17:28:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2F8C208B8 for ; Tue, 27 Oct 2020 17:28:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="jtgqASUv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F2F8C208B8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=UOcXExraZNIAlrpFrZhm3xYnTweq85AlvpH654jBXGo=; b=jtgqASUv91nEU3ogeO/6idr+j 6B6wnpOEMWY15ycz5cfT7FuKMswlQRV+p2GNrU+h4H+5jK3PNsDhepC6Be1Ypy2B8zuO45OjHOeFA WjfvGXvwmp7jKejOnnws6WJ1+TSIUaTBvmIwg2yMSmNq+xmdHpRZMjDAg+jG7/cA5q6mZb4q7oMDi flsqklBwkdyGva22vnuksF7wMQ/N8ax6KFp/fWzCWmciRuchWMXbw2tzUvuZB1QAqUuPhnrV8xkrZ p4+7RiqWK+0FVJojlwnWXiXqHNS03U0que8ROYIqRE26rJRx+9iXZeMvNCljIAPNapmuum0dl8cvO igePZZ82A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXSkf-00055s-Bu; Tue, 27 Oct 2020 17:27:17 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXSjq-0004oT-3l for linux-arm-kernel@lists.infradead.org; Tue, 27 Oct 2020 17:26:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4BCA3150C; Tue, 27 Oct 2020 10:26:25 -0700 (PDT) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 267EF3F719; Tue, 27 Oct 2020 10:26:24 -0700 (PDT) From: Alexandru Elisei To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Subject: [RFC PATCH v3 08/16] KVM: arm64: Add a new VCPU device control group for SPE Date: Tue, 27 Oct 2020 17:26:57 +0000 Message-Id: <20201027172705.15181-9-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.29.1 In-Reply-To: <20201027172705.15181-1-alexandru.elisei@arm.com> References: <20201027172705.15181-1-alexandru.elisei@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_132626_335143_FE1D2CB3 X-CRM114-Status: GOOD ( 27.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, maz@kernel.org, james.morse@arm.com, Sudeep Holla , will@kernel.org, julien.thierry.kdev@gmail.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Sudeep Holla To configure the virtual SPE buffer management interrupt number, we use a VCPU kvm_device ioctl, encapsulating the KVM_ARM_VCPU_SPE_IRQ attribute within the KVM_ARM_VCPU_SPE_CTRL group. After configuring the SPE, userspace is required to call the VCPU ioctl with the attribute KVM_ARM_VCPU_SPE_INIT to initialize SPE on the VCPU. [Alexandru E: Fixed compilation errors, don't allow userspace to set the VCPU feature, removed unused functions, fixed mismatched descriptions, comments and error codes, reworked logic, rebased on top of v5.10-rc1] Signed-off-by: Sudeep Holla Signed-off-by: Alexandru Elisei --- Documentation/virt/kvm/devices/vcpu.rst | 40 ++++++++ arch/arm64/include/uapi/asm/kvm.h | 3 + arch/arm64/kvm/Makefile | 1 + arch/arm64/kvm/guest.c | 9 ++ arch/arm64/kvm/reset.c | 23 +++++ arch/arm64/kvm/spe.c | 129 ++++++++++++++++++++++++ include/kvm/arm_spe.h | 27 +++++ include/uapi/linux/kvm.h | 1 + 8 files changed, 233 insertions(+) create mode 100644 arch/arm64/kvm/spe.c diff --git a/Documentation/virt/kvm/devices/vcpu.rst b/Documentation/virt/kvm/devices/vcpu.rst index 2acec3b9ef65..6135b9827fbe 100644 --- a/Documentation/virt/kvm/devices/vcpu.rst +++ b/Documentation/virt/kvm/devices/vcpu.rst @@ -161,3 +161,43 @@ Specifies the base address of the stolen time structure for this VCPU. The base address must be 64 byte aligned and exist within a valid guest memory region. See Documentation/virt/kvm/arm/pvtime.rst for more information including the layout of the stolen time structure. + +4. GROUP: KVM_ARM_VCPU_SPE_CTRL +=============================== + +:Architectures: ARM64 + +4.1 ATTRIBUTE: KVM_ARM_VCPU_SPE_IRQ +----------------------------------- + +:Parameters: in kvm_device_attr.addr the address for the SPE buffer management + interrupt is a pointer to an int + +Returns: + + ======= ======================================================== + -EBUSY The SPE buffer management interrupt is already set + -EINVAL Invalid SPE overflow interrupt number + -EFAULT Could not read the buffer management interrupt number + -ENXIO SPE not supported or not properly configured + ======= ======================================================== + +A value describing the SPE (Statistical Profiling Extension) overflow interrupt +number for this vcpu. This interrupt should be a PPI and the interrupt type and +number must be same for each vcpu. + +4.2 ATTRIBUTE: KVM_ARM_VCPU_SPE_INIT +------------------------------------ + +:Parameters: no additional parameter in kvm_device_attr.addr + +Returns: + + ======= ====================================================== + -EBUSY SPE already initialized + -ENODEV GIC not initialized + -ENXIO SPE not supported or not properly configured + ======= ====================================================== + +Request the initialization of the SPE. Must be done after initializing the +in-kernel irqchip and after setting the interrupt number for the VCPU. diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index 489e12304dbb..ca57dfb7abf0 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -360,6 +360,9 @@ struct kvm_vcpu_events { #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 #define KVM_ARM_VCPU_PVTIME_CTRL 2 #define KVM_ARM_VCPU_PVTIME_IPA 0 +#define KVM_ARM_VCPU_SPE_CTRL 3 +#define KVM_ARM_VCPU_SPE_IRQ 0 +#define KVM_ARM_VCPU_SPE_INIT 1 /* KVM_IRQ_LINE irq field index values */ #define KVM_ARM_IRQ_VCPU2_SHIFT 28 diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 1504c81fbf5d..f6e76f64ffbe 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -25,3 +25,4 @@ kvm-y := $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o \ vgic/vgic-its.o vgic/vgic-debug.o kvm-$(CONFIG_KVM_ARM_PMU) += pmu-emul.o +kvm-$(CONFIG_KVM_ARM_SPE) += spe.o diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index dfb5218137ca..2ba790eeb782 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -926,6 +926,9 @@ int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_set_attr(vcpu, attr); break; + case KVM_ARM_VCPU_SPE_CTRL: + ret = kvm_arm_spe_set_attr(vcpu, attr); + break; default: ret = -ENXIO; break; @@ -949,6 +952,9 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_get_attr(vcpu, attr); break; + case KVM_ARM_VCPU_SPE_CTRL: + ret = kvm_arm_spe_get_attr(vcpu, attr); + break; default: ret = -ENXIO; break; @@ -972,6 +978,9 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_has_attr(vcpu, attr); break; + case KVM_ARM_VCPU_SPE_CTRL: + ret = kvm_arm_spe_has_attr(vcpu, attr); + break; default: ret = -ENXIO; break; diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index f32490229a4c..4dc205fa4be1 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -87,6 +87,9 @@ int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext) case KVM_CAP_ARM_PTRAUTH_GENERIC: r = system_has_full_ptr_auth(); break; + case KVM_CAP_ARM_SPE: + r = kvm_arm_supports_spe(); + break; default: r = 0; } @@ -223,6 +226,19 @@ static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu) return 0; } +static int kvm_vcpu_enable_spe(struct kvm_vcpu *vcpu) +{ + if (!kvm_arm_supports_spe()) + return -EINVAL; + + /* SPE is disabled if the PE is in AArch32 state */ + if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) + return -EINVAL; + + vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SPE; + return 0; +} + /** * kvm_reset_vcpu - sets core registers and sys_regs to reset value * @vcpu: The VCPU pointer @@ -274,6 +290,13 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) } } + if (test_bit(KVM_ARM_VCPU_SPE, vcpu->arch.features)) { + if (kvm_vcpu_enable_spe(vcpu)) { + ret = -EINVAL; + goto out; + } + } + switch (vcpu->arch.target) { default: if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) { diff --git a/arch/arm64/kvm/spe.c b/arch/arm64/kvm/spe.c new file mode 100644 index 000000000000..f91a52cd7cd3 --- /dev/null +++ b/arch/arm64/kvm/spe.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 ARM Ltd. + */ + +#include +#include +#include + +#include +#include + +static bool kvm_arm_vcpu_supports_spe(struct kvm_vcpu *vcpu) +{ + if (!vcpu_has_spe(vcpu)) + return false; + + if (!irqchip_in_kernel(vcpu->kvm)) + return false; + + return true; +} + +static int kvm_arm_spe_init(struct kvm_vcpu *vcpu) +{ + if (!kvm_arm_spe_irq_initialized(vcpu)) + return -ENXIO; + + if (!vgic_initialized(vcpu->kvm)) + return -ENODEV; + + if (kvm_arm_spe_vcpu_initialized(vcpu)) + return -EBUSY; + + if (kvm_vgic_set_owner(vcpu, vcpu->arch.spe_cpu.irq_num, &vcpu->arch.spe_cpu)) + return -ENXIO; + + vcpu->arch.spe_cpu.initialized = true; + + return 0; +} + +static bool kvm_arm_spe_irq_is_valid(struct kvm *kvm, int irq) +{ + int i; + struct kvm_vcpu *vcpu; + + /* The SPE overflow interrupt can be a PPI only */ + if (!irq_is_ppi(irq)) + return false; + + kvm_for_each_vcpu(i, vcpu, kvm) { + if (!kvm_arm_spe_irq_initialized(vcpu)) + continue; + + if (vcpu->arch.spe_cpu.irq_num != irq) + return false; + } + + return true; +} + +int kvm_arm_spe_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_SPE_IRQ: { + int __user *uaddr = (int __user *)(long)attr->addr; + int irq; + + if (!kvm_arm_vcpu_supports_spe(vcpu)) + return -ENXIO; + + if (get_user(irq, uaddr)) + return -EFAULT; + + if (!kvm_arm_spe_irq_is_valid(vcpu->kvm, irq)) + return -EINVAL; + + if (kvm_arm_spe_irq_initialized(vcpu)) + return -EBUSY; + + kvm_debug("Set kvm ARM SPE irq: %d\n", irq); + vcpu->arch.spe_cpu.irq_num = irq; + + return 0; + } + case KVM_ARM_VCPU_SPE_INIT: + return kvm_arm_spe_init(vcpu); + } + + return -ENXIO; +} + +int kvm_arm_spe_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_SPE_IRQ: { + int __user *uaddr = (int __user *)(long)attr->addr; + int irq; + + if (!kvm_arm_vcpu_supports_spe(vcpu)) + return -ENXIO; + + if (!kvm_arm_spe_irq_initialized(vcpu)) + return -ENXIO; + + irq = vcpu->arch.spe_cpu.irq_num; + if (put_user(irq, uaddr)) + return -EFAULT; + + return 0; + } + } + + return -ENXIO; +} + +int kvm_arm_spe_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_SPE_IRQ: + fallthrough; + case KVM_ARM_VCPU_SPE_INIT: + if (kvm_arm_vcpu_supports_spe(vcpu)) + return 0; + } + + return -ENXIO; +} diff --git a/include/kvm/arm_spe.h b/include/kvm/arm_spe.h index 46ec447ed013..0275e8097529 100644 --- a/include/kvm/arm_spe.h +++ b/include/kvm/arm_spe.h @@ -18,11 +18,38 @@ struct kvm_spe_cpu { bool initialized; /* Feature is initialized on VCPU */ }; +#define kvm_arm_spe_irq_initialized(v) \ + ((v)->arch.spe_cpu.irq_num >= VGIC_NR_SGIS && \ + (v)->arch.spe_cpu.irq_num < VGIC_MAX_PRIVATE) +#define kvm_arm_spe_vcpu_initialized(v) ((v)->arch.spe_cpu.initialized) + +int kvm_arm_spe_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); +int kvm_arm_spe_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); +int kvm_arm_spe_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); + #else #define kvm_arm_supports_spe() false struct kvm_spe_cpu { }; +#define kvm_arm_spe_irq_initialized(v) false +#define kvm_arm_spe_vcpu_initialized(v) false + +static inline int kvm_arm_spe_set_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + return -ENXIO; +} +static inline int kvm_arm_spe_get_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + return -ENXIO; +} +static inline int kvm_arm_spe_has_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + return -ENXIO; +} #endif /* CONFIG_KVM_ARM_SPE */ #endif /* __ASM_ARM_KVM_SPE_H */ diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index ca41220b40b8..96228b823711 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1053,6 +1053,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_X86_USER_SPACE_MSR 188 #define KVM_CAP_X86_MSR_FILTER 189 #define KVM_CAP_ENFORCE_PV_FEATURE_CPUID 190 +#define KVM_CAP_ARM_SPE 191 #ifdef KVM_CAP_IRQ_ROUTING