diff mbox series

[2/2] arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files

Message ID 20201028101123.6293-2-zajec5@gmail.com (mailing list archive)
State New, archived
Headers show
Series [1/2] arm64: add config for Broadcom BCM4908 SoCs | expand

Commit Message

Rafał Miłecki Oct. 28, 2020, 10:11 a.m. UTC 
From: Rafał Miłecki <rafal@milecki.pl>

They don't descibe hardware fully yet but it's enough to boot a system.

Some missing blocks:
1. PMC (Power Management Controller?)
2. Crypto
3. Thermal

Asus misses defining full NAND partitions layout and buttons.

Further changes will fill those gaps as soon as required bindings will
be found / tested / added.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
 arch/arm64/boot/dts/broadcom/Makefile         |   1 +
 arch/arm64/boot/dts/broadcom/bcm4908/Makefile |   2 +
 .../bcm4908/bcm4908-asus-gt-ac5300.dts        |  64 ++++++
 .../boot/dts/broadcom/bcm4908/bcm4908.dtsi    | 182 ++++++++++++++++++
 4 files changed, 249 insertions(+)
 create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/Makefile
 create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
 create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi

Comments

Florian Fainelli Nov. 4, 2020, 3:33 a.m. UTC | #1 
On 10/28/2020 3:11 AM, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal@milecki.pl>
> 
> They don't descibe hardware fully yet but it's enough to boot a system.
> 
> Some missing blocks:
> 1. PMC (Power Management Controller?)
> 2. Crypto
> 3. Thermal
> 
> Asus misses defining full NAND partitions layout and buttons.
> 
> Further changes will fill those gaps as soon as required bindings will
> be found / tested / added.
> 
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
> ---

[snip]

> +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
> @@ -0,0 +1,182 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/dts-v1/;
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		bootargs = "earlycon=bcm63xx_uart,0xff800640";

These bootargs should be dropped from the

> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";

Please drop "arm,cortex-a53"

> +			reg = <0x0>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";
> +			reg = <0x1>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0xfff8>;
> +			next-level-cache = <&l2>;

The device that you have access to did not even ship with a version of PSCI?

> +		};
> +
> +		cpu2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";
> +			reg = <0x2>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0xfff8>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		cpu3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";
> +			reg = <0x3>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0xfff8>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		l2: l2-cache0 {
> +			compatible = "cache";
> +		};
> +	};
> +
> +	gic: interrupt-controller@81000000 {
> +		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;

You would want to create a node that encapsulates the ARM peripheral
addresses within the SoC's physical address range, see
arch/arm/boot/dts/bcm63138.dtsi for an example with the axi bus node.

[snip]

> +
> +			nandcs: nandcs@0 {
> +				compatible = "brcm,nandcs";
> +				reg = <0>;
> +				nand-on-flash-bbt;
> +				brcm,nand-has-wp;

Those last two properties should be moved to the board level DTS file.

> +			};
> +		};
> +
> +		reboot {
> +			compatible = "syscon-reboot";
> +			regmap = <&timer>;
> +			offset = <0x34>;
> +			mask = <1>;
> +		};
> +	};
> +};
>
Rafał Miłecki Nov. 4, 2020, 8:02 a.m. UTC | #2 
On 04.11.2020 04:33, Florian Fainelli wrote:
> On 10/28/2020 3:11 AM, Rafał Miłecki wrote:
>> From: Rafał Miłecki <rafal@milecki.pl>
>>
>> They don't descibe hardware fully yet but it's enough to boot a system.
>>
>> Some missing blocks:
>> 1. PMC (Power Management Controller?)
>> 2. Crypto
>> 3. Thermal
>>
>> Asus misses defining full NAND partitions layout and buttons.
>>
>> Further changes will fill those gaps as soon as required bindings will
>> be found / tested / added.
>>
>> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
>> ---
> 
> [snip]
> 
>> +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
>> @@ -0,0 +1,182 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/dts-v1/;
>> +
>> +/ {
>> +	interrupt-parent = <&gic>;
>> +
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	aliases {
>> +		serial0 = &uart0;
>> +	};
>> +
>> +	chosen {
>> +		bootargs = "earlycon=bcm63xx_uart,0xff800640";
> 
> These bootargs should be dropped from the

Can you explain why, is that some kernel rule I missed? That's extremely helpful for debugging.


>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu0: cpu@0 {
>> +			device_type = "cpu";
>> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";
> 
> Please drop "arm,cortex-a53"
> 
>> +			reg = <0x0>;
>> +			next-level-cache = <&l2>;
>> +		};
>> +
>> +		cpu1: cpu@1 {
>> +			device_type = "cpu";
>> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";
>> +			reg = <0x1>;
>> +			enable-method = "spin-table";
>> +			cpu-release-addr = <0x0 0xfff8>;
>> +			next-level-cache = <&l2>;
> 
> The device that you have access to did not even ship with a version of PSCI?

Whenever trying to use psci defined as:

psci {
	compatible = "arm,psci-0.2";
	method = "smc";
};

(with updated enable-method) I get:

psci: probing for conduit method from DT.
------------[ cut here ]------------
kernel BUG at arch/arm64/kernel/traps.c:406!
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
CPU: 0 PID: 0 Comm: swapper Not tainted 5.10.0-rc2 #3
Hardware name: Asus GT-AC5300 (DT)
pstate: 00000085 (nzcv daIf -PAN -UAO -TCO BTYPE=--)
pc : do_undefinstr+0x2d8/0x300
lr : do_undefinstr+0x2e4/0x300
sp : ffffffc010933c60
x29: ffffffc010933c60 x28: ffffffc01093b680
x27: ffffffc0107a4c40 x26: ffffffc0107bcca0
x25: ffffffc010953c28 x24: 0000000000000080
x23: 0000000080000085 x22: ffffffc01099e100
x21: 00000000d4000003 x20: ffffffc01093b680
x19: ffffffc010933cd0 x18: ffffffc010942fd0
x17: 0000000000001400 x16: 0000000000001c00
x15: fffffffeffe00000 x14: ffffffffffffffff
x13: 0000000000000038 x12: 0101010101010101
x11: 0000000000000004 x10: 0101010101010101
x9 : 0000000000000004 x8 : 0000000000000004
x7 : 0000000000000000 x6 : ffffffc010933cb8
x5 : ffffffc010933cb8 x4 : ffffffc01093cf58
x3 : 0000000000000001 x2 : 0000000000000000
x1 : ffffffc01093b680 x0 : 0000000080000085
Call trace:
  do_undefinstr+0x2d8/0x300
  el1_sync_handler+0xbc/0x140
  el1_sync+0x80/0x100
  __arm_smccc_smc+0x0/0x2c
  psci_probe+0x34/0x2c4
  psci_0_2_init+0x18/0x24
  psci_dt_init+0x64/0x8c
  setup_arch+0x428/0x5c4
  start_kernel+0x78/0x52c
Code: 17ffffa7 f9401bf7 17ffff80 f9001bf7 (d4210000)
random: get_random_bytes called from print_oops_end_marker+0x2c/0x70 with crng_init=0
---[ end trace 0000000000000000 ]---
Kernel panic - not syncing: Attempted to kill the idle task!


>> +		};
>> +
>> +		cpu2: cpu@2 {
>> +			device_type = "cpu";
>> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";
>> +			reg = <0x2>;
>> +			enable-method = "spin-table";
>> +			cpu-release-addr = <0x0 0xfff8>;
>> +			next-level-cache = <&l2>;
>> +		};
>> +
>> +		cpu3: cpu@3 {
>> +			device_type = "cpu";
>> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";
>> +			reg = <0x3>;
>> +			enable-method = "spin-table";
>> +			cpu-release-addr = <0x0 0xfff8>;
>> +			next-level-cache = <&l2>;
>> +		};
>> +
>> +		l2: l2-cache0 {
>> +			compatible = "cache";
>> +		};
>> +	};
>> +
>> +	gic: interrupt-controller@81000000 {
>> +		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>> +		#interrupt-cells = <3>;
>> +		#address-cells = <0>;
> 
> You would want to create a node that encapsulates the ARM peripheral
> addresses within the SoC's physical address range, see
> arch/arm/boot/dts/bcm63138.dtsi for an example with the axi bus node.
> 
> [snip]
> 
>> +
>> +			nandcs: nandcs@0 {
>> +				compatible = "brcm,nandcs";
>> +				reg = <0>;
>> +				nand-on-flash-bbt;
>> +				brcm,nand-has-wp;
> 
> Those last two properties should be moved to the board level DTS file.
> 
>> +			};
>> +		};
>> +
>> +		reboot {
>> +			compatible = "syscon-reboot";
>> +			regmap = <&timer>;
>> +			offset = <0x34>;
>> +			mask = <1>;
>> +		};
>> +	};
>> +};
Robin Murphy Nov. 4, 2020, 10:35 a.m. UTC | #3 
On 2020-10-28 10:11, Rafał Miłecki wrote:
[...]
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";

Erm, there's no binding for that - did you mean "brcm,brahma-b53"?

> +			reg = <0x0>;
> +			next-level-cache = <&l2>;
> +		};
[...]
> +	gic: interrupt-controller@81000000 {
> +		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";

There's really no logical reason for a 64-bit system to pretend to be 
compatible with Cortex-A9. This is presumably GIC-400 (or maybe GIC-500) 
so it would be better to describe it as what it is.

> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +		interrupt-controller;
> +		reg = <0x00 0x81001000 0x00 0x1000>, <0x00 0x81002000 0x00 0x2000>;
> +	};
[...]
> +	pmu {
> +		compatible = "arm,armv8-pmuv3";

Use the appropriate compatible for the actual CPUs - this is real 
hardware, not a software model.

Robin.

> +		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> +	};
Rafał Miłecki Nov. 4, 2020, 12:07 p.m. UTC | #4 
On 04.11.2020 11:35, Robin Murphy wrote:
> On 2020-10-28 10:11, Rafał Miłecki wrote:
> [...]
>> +        cpu0: cpu@0 {
>> +            device_type = "cpu";
>> +            compatible = "brcm,cortex-b53", "arm,cortex-a53";
> 
> Erm, there's no binding for that - did you mean "brcm,brahma-b53"?

I'm not sure if that's the same thing. Unfortunately I don't have access to
any Broadcom documentation.

Florian: could you try to verify that, please?


>> +            reg = <0x0>;
>> +            next-level-cache = <&l2>;
>> +        };
> [...]
>> +    gic: interrupt-controller@81000000 {
>> +        compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
> 
> There's really no logical reason for a 64-bit system to pretend to be compatible with Cortex-A9. This is presumably GIC-400 (or maybe GIC-500) so it would be better to describe it as what it is.

Right, sorry, I'm totally new to the arm64. I just found that working and
noticed few boards using it. They may require tweaking too probably:

$ grep "arm,cortex-a.*-gic" arch/arm64/boot/dts/*/*.dts*
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi:              compatible = "arm,gic-400", "arm,cortex-a15-gic";
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi:           compatible = "arm,gic-400", "arm,cortex-a15-gic";
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi:             compatible = "arm,cortex-a15-gic";
arch/arm64/boot/dts/apm/apm-storm.dtsi:         compatible = "arm,cortex-a15-gic";
arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi:               compatible = "arm,gic-400", "arm,cortex-a15-gic";
arch/arm64/boot/dts/arm/juno-base.dtsi:         compatible = "arm,gic-400", "arm,cortex-a15-gic";
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts:             compatible = "arm,gic-400", "arm,cortex-a15-gic";
arch/arm64/boot/dts/freescale/s32v234.dtsi:             compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:          compatible = "arm,gic-400", "arm,cortex-a15-gic";
arch/arm64/boot/dts/nvidia/tegra132.dtsi:               compatible = "arm,cortex-a15-gic";


>> +        #interrupt-cells = <3>;
>> +        #address-cells = <0>;
>> +        interrupt-controller;
>> +        reg = <0x00 0x81001000 0x00 0x1000>, <0x00 0x81002000 0x00 0x2000>;
>> +    };
> [...]
>> +    pmu {
>> +        compatible = "arm,armv8-pmuv3";
> 
> Use the appropriate compatible for the actual CPUs - this is real hardware, not a software model.

Thanks!


>> +        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> +                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> +                 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> +                 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> +        interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
>> +    };
Rafał Miłecki Nov. 4, 2020, 12:21 p.m. UTC | #5 
On 04.11.2020 04:33, Florian Fainelli wrote:
>> +	gic: interrupt-controller@81000000 {
>> +		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>> +		#interrupt-cells = <3>;
>> +		#address-cells = <0>;
> 
> You would want to create a node that encapsulates the ARM peripheral
> addresses within the SoC's physical address range, see
> arch/arm/boot/dts/bcm63138.dtsi for an example with the axi bus node.
> 
> [snip]

As a general note: putting interrupt-controller directly in the root node
seems to be (incorrectly I assume) done in about 1/3 of arm64 DTS files.

Guessing by indention level:

 > egrep $'^\t[a-z].*interrupt-controller' arch/arm64/boot/dts/*/*.dts* | wc -l
66

Just in case someone is looking for a minor cleanup task.
Florian Fainelli Nov. 4, 2020, 3:09 p.m. UTC | #6 
On 11/4/2020 4:07 AM, Rafał Miłecki wrote:
> On 04.11.2020 11:35, Robin Murphy wrote:
>> On 2020-10-28 10:11, Rafał Miłecki wrote:
>> [...]
>>> +        cpu0: cpu@0 {
>>> +            device_type = "cpu";
>>> +            compatible = "brcm,cortex-b53", "arm,cortex-a53";
>>
>> Erm, there's no binding for that - did you mean "brcm,brahma-b53"?
> 
> I'm not sure if that's the same thing. Unfortunately I don't have access to
> any Broadcom documentation.
> 
> Florian: could you try to verify that, please?

It should be "brcm,brahma-b53", that is the CPU design that this SoC uses.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
index cb7de8d99223..998e240aa698 100644
--- a/arch/arm64/boot/dts/broadcom/Makefile
+++ b/arch/arm64/boot/dts/broadcom/Makefile
@@ -5,5 +5,6 @@  dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \
 			      bcm2837-rpi-3-b-plus.dtb \
 			      bcm2837-rpi-cm3-io3.dtb
 
+subdir-y	+= bcm4908
 subdir-y	+= northstar2
 subdir-y	+= stingray
diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
new file mode 100644
index 000000000000..ef26c23603ce
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
@@ -0,0 +1,2 @@ 
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb
diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
new file mode 100644
index 000000000000..9b87aab5f8b2
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
@@ -0,0 +1,64 @@ 
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "bcm4908.dtsi"
+
+/ {
+	compatible = "asus,gt-ac5300", "brcm,bcm4908";
+	model = "Asus GT-AC5300";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00 0x00 0x00 0x40000000>;
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		wifi {
+			label = "WiFi";
+			linux,code = <KEY_RFKILL>;
+			gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+		};
+
+		wps {
+			label = "WPS";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+		};
+
+		restart {
+			label = "Reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+		};
+
+		brightness {
+			label = "LEDs";
+			linux,code = <KEY_BRIGHTNESS_ZERO>;
+			gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&nandcs {
+	nand-ecc-strength = <4>;
+	nand-ecc-step-size = <512>;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "cferom";
+			reg = <0x000000000000 0x000000100000>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
new file mode 100644
index 000000000000..af87a844ad82
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
@@ -0,0 +1,182 @@ 
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+	interrupt-parent = <&gic>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		bootargs = "earlycon=bcm63xx_uart,0xff800640";
+		stdout-path = "serial0:115200n8";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "brcm,cortex-b53", "arm,cortex-a53";
+			reg = <0x0>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "brcm,cortex-b53", "arm,cortex-a53";
+			reg = <0x1>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xfff8>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "brcm,cortex-b53", "arm,cortex-a53";
+			reg = <0x2>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xfff8>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "brcm,cortex-b53", "arm,cortex-a53";
+			reg = <0x3>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xfff8>;
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	gic: interrupt-controller@81000000 {
+		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x00 0x81001000 0x00 0x1000>, <0x00 0x81002000 0x00 0x2000>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	clocks {
+		periph_clk: periph_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			clock-output-names = "periph";
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x80000000 0x10000>;
+
+		ehci@c300 {
+			compatible = "generic-ehci";
+			reg = <0xc300 0x100>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		ohci@c400 {
+			compatible = "generic-ohci";
+			reg = <0xc400 0x100>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		xhci@d000 {
+			compatible = "generic-xhci";
+			reg = <0xd000 0x8c8>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+	};
+
+	ubus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0xff800000 0x3000>;
+
+		timer: timer@400 {
+			compatible = "brcm,bcm6328-timer", "syscon";
+			reg = <0x400 0x3c>;
+		};
+
+		gpio0: gpio-controller@500 {
+			compatible = "brcm,bcm6345-gpio";
+			reg-names = "dirout", "dat";
+			reg = <0x500 0x28>, <0x528 0x28>;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+		};
+
+		uart0: serial@640 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x640 0x18>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&periph_clk>;
+			clock-names = "periph";
+			status = "okay";
+		};
+
+		nand@1800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
+			reg = <0x1800 0x600>, <0x2000 0x10>;
+			reg-names = "nand", "nand-int-base";
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "nand";
+			status = "okay";
+
+			nandcs: nandcs@0 {
+				compatible = "brcm,nandcs";
+				reg = <0>;
+				nand-on-flash-bbt;
+				brcm,nand-has-wp;
+			};
+		};
+
+		reboot {
+			compatible = "syscon-reboot";
+			regmap = <&timer>;
+			offset = <0x34>;
+			mask = <1>;
+		};
+	};
+};