| Message ID | 20201028220945.3826358-15-suzuki.poulose@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: Support for ETM system instructions | expand |
On Wed, Oct 28, 2020 at 10:09:32PM +0000, Suzuki K Poulose wrote: > As we are about define a switch..case table for individual register > access by offset for implementing the system instruction support, > document the possible set of registers for each group to make > it easier to co-relate. > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Mike Leach <mike.leach@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x.h | 21 ++++++++++++------- > 1 file changed, 13 insertions(+), 8 deletions(-) Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> I'm done for today and will continue tomorrow. Thanks, Mathieu > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 14e0f29db6b3..510828c73db6 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -44,13 +44,13 @@ > #define TRCVDSACCTLR 0x0A4 > #define TRCVDARCCTLR 0x0A8 > /* Derived resources registers */ > -#define TRCSEQEVRn(n) (0x100 + (n * 4)) > +#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ > #define TRCSEQRSTEVR 0x118 > #define TRCSEQSTR 0x11C > #define TRCEXTINSELR 0x120 > -#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) > -#define TRCCNTCTLRn(n) (0x150 + (n * 4)) > -#define TRCCNTVRn(n) (0x160 + (n * 4)) > +#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ > +#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ > +#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ > /* ID registers */ > #define TRCIDR8 0x180 > #define TRCIDR9 0x184 > @@ -59,7 +59,7 @@ > #define TRCIDR12 0x190 > #define TRCIDR13 0x194 > #define TRCIMSPEC0 0x1C0 > -#define TRCIMSPECn(n) (0x1C0 + (n * 4)) > +#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ > #define TRCIDR0 0x1E0 > #define TRCIDR1 0x1E4 > #define TRCIDR2 0x1E8 > @@ -68,9 +68,12 @@ > #define TRCIDR5 0x1F4 > #define TRCIDR6 0x1F8 > #define TRCIDR7 0x1FC > -/* Resource selection registers */ > +/* > + * Resource selection registers, n = 2-31. > + * First pair (regs 0, 1) is always present and is reserved. > + */ > #define TRCRSCTLRn(n) (0x200 + (n * 4)) > -/* Single-shot comparator registers */ > +/* Single-shot comparator registers, n = 0-7 */ > #define TRCSSCCRn(n) (0x280 + (n * 4)) > #define TRCSSCSRn(n) (0x2A0 + (n * 4)) > #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) > @@ -80,11 +83,13 @@ > #define TRCPDCR 0x310 > #define TRCPDSR 0x314 > /* Trace registers (0x318-0xEFC) */ > -/* Comparator registers */ > +/* Address Comparator registers n = 0-15 */ > #define TRCACVRn(n) (0x400 + (n * 8)) > #define TRCACATRn(n) (0x480 + (n * 8)) > +/* Data Value Comparator Value registers, n = 0-7 */ > #define TRCDVCVRn(n) (0x500 + (n * 16)) > #define TRCDVCMRn(n) (0x580 + (n * 16)) > +/* ContextID/Virtual ContextID comparators, n = 0-7 */ > #define TRCCIDCVRn(n) (0x600 + (n * 8)) > #define TRCVMIDCVRn(n) (0x640 + (n * 8)) > #define TRCCIDCCTLR0 0x680 > -- > 2.24.1 >
On Wed, 28 Oct 2020 at 16:10, Suzuki K Poulose <suzuki.poulose@arm.com> wrote: > > As we are about define a switch..case table for individual register > access by offset for implementing the system instruction support, > document the possible set of registers for each group to make > it easier to co-relate. s/co-relate/correlate > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Mike Leach <mike.leach@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x.h | 21 ++++++++++++------- > 1 file changed, 13 insertions(+), 8 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 14e0f29db6b3..510828c73db6 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -44,13 +44,13 @@ > #define TRCVDSACCTLR 0x0A4 > #define TRCVDARCCTLR 0x0A8 > /* Derived resources registers */ > -#define TRCSEQEVRn(n) (0x100 + (n * 4)) > +#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ > #define TRCSEQRSTEVR 0x118 > #define TRCSEQSTR 0x11C > #define TRCEXTINSELR 0x120 > -#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) > -#define TRCCNTCTLRn(n) (0x150 + (n * 4)) > -#define TRCCNTVRn(n) (0x160 + (n * 4)) > +#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ > +#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ > +#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ > /* ID registers */ > #define TRCIDR8 0x180 > #define TRCIDR9 0x184 > @@ -59,7 +59,7 @@ > #define TRCIDR12 0x190 > #define TRCIDR13 0x194 > #define TRCIMSPEC0 0x1C0 > -#define TRCIMSPECn(n) (0x1C0 + (n * 4)) > +#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ > #define TRCIDR0 0x1E0 > #define TRCIDR1 0x1E4 > #define TRCIDR2 0x1E8 > @@ -68,9 +68,12 @@ > #define TRCIDR5 0x1F4 > #define TRCIDR6 0x1F8 > #define TRCIDR7 0x1FC > -/* Resource selection registers */ > +/* > + * Resource selection registers, n = 2-31. > + * First pair (regs 0, 1) is always present and is reserved. > + */ > #define TRCRSCTLRn(n) (0x200 + (n * 4)) > -/* Single-shot comparator registers */ > +/* Single-shot comparator registers, n = 0-7 */ > #define TRCSSCCRn(n) (0x280 + (n * 4)) > #define TRCSSCSRn(n) (0x2A0 + (n * 4)) > #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) > @@ -80,11 +83,13 @@ > #define TRCPDCR 0x310 > #define TRCPDSR 0x314 > /* Trace registers (0x318-0xEFC) */ > -/* Comparator registers */ > +/* Address Comparator registers n = 0-15 */ > #define TRCACVRn(n) (0x400 + (n * 8)) > #define TRCACATRn(n) (0x480 + (n * 8)) > +/* Data Value Comparator Value registers, n = 0-7 */ > #define TRCDVCVRn(n) (0x500 + (n * 16)) > #define TRCDVCMRn(n) (0x580 + (n * 16)) > +/* ContextID/Virtual ContextID comparators, n = 0-7 */ > #define TRCCIDCVRn(n) (0x600 + (n * 8)) > #define TRCVMIDCVRn(n) (0x640 + (n * 8)) > #define TRCCIDCCTLR0 0x680 > -- > 2.24.1 >
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 14e0f29db6b3..510828c73db6 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -44,13 +44,13 @@ #define TRCVDSACCTLR 0x0A4 #define TRCVDARCCTLR 0x0A8 /* Derived resources registers */ -#define TRCSEQEVRn(n) (0x100 + (n * 4)) +#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ #define TRCSEQRSTEVR 0x118 #define TRCSEQSTR 0x11C #define TRCEXTINSELR 0x120 -#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) -#define TRCCNTCTLRn(n) (0x150 + (n * 4)) -#define TRCCNTVRn(n) (0x160 + (n * 4)) +#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ +#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ +#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ /* ID registers */ #define TRCIDR8 0x180 #define TRCIDR9 0x184 @@ -59,7 +59,7 @@ #define TRCIDR12 0x190 #define TRCIDR13 0x194 #define TRCIMSPEC0 0x1C0 -#define TRCIMSPECn(n) (0x1C0 + (n * 4)) +#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ #define TRCIDR0 0x1E0 #define TRCIDR1 0x1E4 #define TRCIDR2 0x1E8 @@ -68,9 +68,12 @@ #define TRCIDR5 0x1F4 #define TRCIDR6 0x1F8 #define TRCIDR7 0x1FC -/* Resource selection registers */ +/* + * Resource selection registers, n = 2-31. + * First pair (regs 0, 1) is always present and is reserved. + */ #define TRCRSCTLRn(n) (0x200 + (n * 4)) -/* Single-shot comparator registers */ +/* Single-shot comparator registers, n = 0-7 */ #define TRCSSCCRn(n) (0x280 + (n * 4)) #define TRCSSCSRn(n) (0x2A0 + (n * 4)) #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) @@ -80,11 +83,13 @@ #define TRCPDCR 0x310 #define TRCPDSR 0x314 /* Trace registers (0x318-0xEFC) */ -/* Comparator registers */ +/* Address Comparator registers n = 0-15 */ #define TRCACVRn(n) (0x400 + (n * 8)) #define TRCACATRn(n) (0x480 + (n * 8)) +/* Data Value Comparator Value registers, n = 0-7 */ #define TRCDVCVRn(n) (0x500 + (n * 16)) #define TRCDVCMRn(n) (0x580 + (n * 16)) +/* ContextID/Virtual ContextID comparators, n = 0-7 */ #define TRCCIDCVRn(n) (0x600 + (n * 8)) #define TRCVMIDCVRn(n) (0x640 + (n * 8)) #define TRCCIDCCTLR0 0x680
As we are about define a switch..case table for individual register access by offset for implementing the system instruction support, document the possible set of registers for each group to make it easier to co-relate. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- drivers/hwtracing/coresight/coresight-etm4x.h | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-)