| Message ID | 20201031182137.1879521-7-contact@paulk.fr (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Allwinner V3 SL631 Action Camera Support and Related Fixes | expand |
On Sat, Oct 31, 2020 at 07:21:34PM +0100, Paul Kocialkowski wrote: > The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209. > Its address follows the sytsem controller block, which was previously > incorrectly described as spanning over 0x1000 address bytes. Is it after, or right in the middle of it? Maxime
Hi, On Mon 02 Nov 20, 11:12, Maxime Ripard wrote: > On Sat, Oct 31, 2020 at 07:21:34PM +0100, Paul Kocialkowski wrote: > > The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209. > > Its address follows the sytsem controller block, which was previously > > incorrectly described as spanning over 0x1000 address bytes. > > Is it after, or right in the middle of it? That's up for interpretation actually: - The V3 datasheet mentions that System Control is 0x01C00000 --- 0x01C00FFF; - In practice, sunxi_sram.c uses a regmap with max_reg set to 0x30 for the V3s/H3 so this gives us some room. Looking at other SoCs with the same setup (take sun8i-r40 for instance), system-control is limited to 0x30 and the NMI controller follows it. In the case of R40, the SRAM controlled is also said to be 4K-long in the Allwinner docs. So all in all, this leads me to believe that the system-controller instance stops well before 0x1c000d0 on the V3s as well. Otherwise, we should also make the R40 consistent. Cheers, Paul
On Mon, Nov 02, 2020 at 11:25:22AM +0100, Paul Kocialkowski wrote: > Hi, > > On Mon 02 Nov 20, 11:12, Maxime Ripard wrote: > > On Sat, Oct 31, 2020 at 07:21:34PM +0100, Paul Kocialkowski wrote: > > > The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209. > > > Its address follows the sytsem controller block, which was previously > > > incorrectly described as spanning over 0x1000 address bytes. > > > > Is it after, or right in the middle of it? > > That's up for interpretation actually: > - The V3 datasheet mentions that System Control is 0x01C00000 --- 0x01C00FFF; > - In practice, sunxi_sram.c uses a regmap with max_reg set to 0x30 for the > V3s/H3 so this gives us some room. > > Looking at other SoCs with the same setup (take sun8i-r40 for instance), > system-control is limited to 0x30 and the NMI controller follows it. > In the case of R40, the SRAM controlled is also said to be 4K-long in the > Allwinner docs. > > So all in all, this leads me to believe that the system-controller instance > stops well before 0x1c000d0 on the V3s as well. Otherwise, we should also > make the R40 consistent. That's a bit unfortunate, but yeah, I guess we want to remain consistent here. Maxime
On Mon 02 Nov 20, 14:44, Maxime Ripard wrote: > On Mon, Nov 02, 2020 at 11:25:22AM +0100, Paul Kocialkowski wrote: > > Hi, > > > > On Mon 02 Nov 20, 11:12, Maxime Ripard wrote: > > > On Sat, Oct 31, 2020 at 07:21:34PM +0100, Paul Kocialkowski wrote: > > > > The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209. > > > > Its address follows the sytsem controller block, which was previously > > > > incorrectly described as spanning over 0x1000 address bytes. > > > > > > Is it after, or right in the middle of it? > > > > That's up for interpretation actually: > > - The V3 datasheet mentions that System Control is 0x01C00000 --- 0x01C00FFF; > > - In practice, sunxi_sram.c uses a regmap with max_reg set to 0x30 for the > > V3s/H3 so this gives us some room. > > > > Looking at other SoCs with the same setup (take sun8i-r40 for instance), > > system-control is limited to 0x30 and the NMI controller follows it. > > In the case of R40, the SRAM controlled is also said to be 4K-long in the > > Allwinner docs. > > > > So all in all, this leads me to believe that the system-controller instance > > stops well before 0x1c000d0 on the V3s as well. Otherwise, we should also > > make the R40 consistent. > > That's a bit unfortunate, but yeah, I guess we want to remain consistent here. Honestly I think the Allwinner docs are plain wrong on this one. IIRC they used to describe the NMI as a separate controller in the memory map. I think they just overlook it now and copy/paste 4K size for each controller regardless of the actual hardware, so I'm not very worried. Cheers, Pauls
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 7b2d684aeb97..d2e2abd3869a 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -157,12 +157,20 @@ mixer0_out_tcon0: endpoint { syscon: system-control@1c00000 { compatible = "allwinner,sun8i-v3s-system-control", "allwinner,sun8i-h3-system-control"; - reg = <0x01c00000 0x1000>; + reg = <0x01c00000 0xd0>; #address-cells = <1>; #size-cells = <1>; ranges; }; + nmi_intc: interrupt-controller@1c000d0 { + compatible = "allwinner,sun8i-v3s-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c000d0 0x0c>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + }; + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-v3s-tcon"; reg = <0x01c0c000 0x1000>;
The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209. Its address follows the sytsem controller block, which was previously incorrectly described as spanning over 0x1000 address bytes. This reduces the system controller address span up to the NMI controller and adds a node for the controller, with its dedicated compatible. While the interrupt number was found in Allwinner's documentation, the address for the controller is specified in any Allwinner SDK supporting sun8iw8 (V3/V3s) at: drivers/power/axp_power/axp20/axp20-board.c It was tested to work on a V3 board with an AXP209 connected to the NMI interrupt line. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)