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Mon, 2 Nov 2020 04:12:04 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ABtuY059084; Mon, 2 Nov 2020 04:12:01 -0600 From: Kishon Vijay Abraham I To: Lee Jones , Rob Herring , Bjorn Helgaas , Tero Kristo , Nishanth Menon Subject: [PATCH 1/8] dt-bindings: mfd: ti, j721e-system-controller.yaml: Document "pcie-ctrl" Date: Mon, 2 Nov 2020 15:41:47 +0530 Message-ID: <20201102101154.13598-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201102101154.13598-1-kishon@ti.com> References: <20201102101154.13598-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201102_051231_196302_4FC28AD4 X-CRM114-Status: GOOD ( 11.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roger Quadros Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add binding documentation for "pcie-ctrl" which should be a subnode of the system controller. Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/mfd/ti,j721e-system-controller.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml index 19fcf59fd2fe..fd985794e419 100644 --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml @@ -50,6 +50,12 @@ patternProperties: specified in Documentation/devicetree/bindings/mux/reg-mux.txt + "^pcie-ctrl@[0-9a-f]+$": + type: object + description: | + This is the PCIe controller configuration required to configre PCIe + mode, lane width and speed. + required: - compatible - reg